From patchwork Fri Jun 30 13:48:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luis Machado X-Patchwork-Id: 71918 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id BBEB73882645 for ; Fri, 30 Jun 2023 13:50:40 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org BBEB73882645 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1688133040; bh=YF0DAGV3cRBxH8u3KAyC3fA5NwUco12p1hlPlj5TFtw=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=AaeiiSrFrDi29rLcKa6oypO6bPYwNL83qzYFB6SdOWna+6snflOQfgmmsRvcMFtzL krDU8u/O+d7PA0MSW3Uv3A7FL5C9Tl6H6GEYGjyCbjLqT+24LFT52VkSqLYiuDCUAG /B6F3M2OsP6DUBABugx5F7Z0T2plwc2g8TrDy12c= X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from EUR05-DB8-obe.outbound.protection.outlook.com (mail-db8eur05on2087.outbound.protection.outlook.com [40.107.20.87]) by sourceware.org (Postfix) with ESMTPS id 293883884598 for ; Fri, 30 Jun 2023 13:49:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 293883884598 Received: from DU2PR04CA0198.eurprd04.prod.outlook.com (2603:10a6:10:28d::23) by AS8PR08MB8565.eurprd08.prod.outlook.com (2603:10a6:20b:568::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6521.26; Fri, 30 Jun 2023 13:49:05 +0000 Received: from DBAEUR03FT033.eop-EUR03.prod.protection.outlook.com (2603:10a6:10:28d:cafe::e0) by DU2PR04CA0198.outlook.office365.com (2603:10a6:10:28d::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6544.22 via Frontend Transport; Fri, 30 Jun 2023 13:49:05 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by DBAEUR03FT033.mail.protection.outlook.com (100.127.142.251) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6544.22 via Frontend Transport; Fri, 30 Jun 2023 13:49:05 +0000 Received: ("Tessian outbound d6c4ee3ba1eb:v142"); Fri, 30 Jun 2023 13:49:05 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: 7840ed9cd422b210 X-CR-MTA-TID: 64aa7808 Received: from c03d9f0ac955.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id C804B39D-AD32-4019-884C-E7455DCD18F8.1; Fri, 30 Jun 2023 13:48:58 +0000 Received: from EUR02-AM0-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id c03d9f0ac955.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Fri, 30 Jun 2023 13:48:58 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=QjnKuw9J2fvNB9k/8SvDTE7K7qsLxMAlpWrez9YxJazgPjPAqa7j7hqreXLyFJx/5QnA3sNgydg7iX9un4IwFoQLH9V9OWe3Uo5H89U5A7iL8VqPYv99rrxPePMTVSqj3rJnPLvarKOi6qyJIsa9unL72Po65ANohsKs6QfQXMef8qz8gw2+8JNxpSvalPfFVbMSkwbklmB3u1zIZ7oeuDvhSdER5Cu6NsiFg2nvuj+mjeV8KIchzeAkYHXN4BJH/h+m1kWFI1d76OmhVLmjvapk+SKDly2mN1Xt8hnQcL2AAC6GJupPK2/aFrZ0CptttoOMC0evpk3vyUjhFU3tpw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=YF0DAGV3cRBxH8u3KAyC3fA5NwUco12p1hlPlj5TFtw=; b=JjmhODZ4nW5iiR70ENOH6bhab7OAX2LHxr2Wm8gOxKPuh2lTM7Bm21bp1bzjgsQ01EGq1d1EuLFDdYI9x8QxI5TtdRjydIh7bZ1LbRP75f8e6l4D3DvB1JSYUNa/+19QeIZZQm/Z//HO+mWcUp6ciSN/NDNqWeR4zWYHR/85is4ydCHm2hDfC5eAVA2Q398X7xIeLT6VxMMgMe/EdD2iiXx/lVJc6IwSjc7EV2IGmHx2vDG8vsrB/Qq9nOYkWFfuAFO3b7j2OmXvg7O/u98DAm3m20i+jNRi3SedAxMMFhMZ0tNGPgOJOC7HHX13jO+XAaV3b+/JaKy8ndgdXC0rLg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 40.67.248.234) smtp.rcpttodomain=sourceware.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=none (message not signed); arc=none Received: from AS8PR05CA0007.eurprd05.prod.outlook.com (2603:10a6:20b:311::12) by GV2PR08MB9160.eurprd08.prod.outlook.com (2603:10a6:150:e0::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6544.19; Fri, 30 Jun 2023 13:48:56 +0000 Received: from AM7EUR03FT063.eop-EUR03.prod.protection.outlook.com (2603:10a6:20b:311:cafe::be) by AS8PR05CA0007.outlook.office365.com (2603:10a6:20b:311::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6544.22 via Frontend Transport; Fri, 30 Jun 2023 13:48:55 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 40.67.248.234) smtp.mailfrom=arm.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; pr=C Received: from nebula.arm.com (40.67.248.234) by AM7EUR03FT063.mail.protection.outlook.com (100.127.140.221) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6544.22 via Frontend Transport; Fri, 30 Jun 2023 13:48:55 +0000 Received: from AZ-NEU-EX02.Emea.Arm.com (10.251.26.5) by AZ-NEU-EX03.Arm.com (10.251.24.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Fri, 30 Jun 2023 13:48:54 +0000 Received: from AZ-NEU-EX03.Arm.com (10.251.24.31) by AZ-NEU-EX02.Emea.Arm.com (10.251.26.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Fri, 30 Jun 2023 13:48:54 +0000 Received: from e129171.arm.com (10.57.27.17) by mail.arm.com (10.251.24.31) with Microsoft SMTP Server id 15.1.2507.27 via Frontend Transport; Fri, 30 Jun 2023 13:48:53 +0000 To: Subject: [PATCH 5/6] [gdb/testsuite] sme2: Extend SME tests to include SME2 Date: Fri, 30 Jun 2023 14:48:43 +0100 Message-ID: <20230630134844.1238445-6-luis.machado@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230630134844.1238445-1-luis.machado@arm.com> References: <20230630134844.1238445-1-luis.machado@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AM7EUR03FT063:EE_|GV2PR08MB9160:EE_|DBAEUR03FT033:EE_|AS8PR08MB8565:EE_ X-MS-Office365-Filtering-Correlation-Id: c683cf2c-3174-45bd-76cf-08db7970c543 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: 352McGZ8utFT7hnDtr06f61SvftyDEdLZfbNpYVgfi2UwVyGnLPfyle9uHTRBvyc5meBSS36wX2nYymhhe3BoKpiSp3vMHcMRN19HGQLqMXM1yor/dnhEsWL7pGGXBMVgoDgkxJlwh+k2TbZjsPPF9BmXsjFT5SoLPEP4YU6cdqPWbssd0fmRnskcAclAueJVTFWvnB7IFo8fKlbe0AUPGDZa+c/NqQFXufz2fiMXZJ4VKW7es17S9ndTFvosC6HCHsN5Rh9FPhiTGTPsd/Zk3Tp7oX4htmpBJl3Z24exg6bTBNsk2UEh/aQ59VECM1uItEvrBG9viKsaeJh4Ly1a9TsZU5lniUlZNaYVqS684JD08GaN9kFU/wBZORwhO+xC2GaN3bpnajGgpL3Zj8V5i3tGMV5clWFjYSMNSVUk9VtDVSAr5w2uKJi836qBs5bnaoc+rSUoweUDm7SlEzRkEDGyp7MxeNQYp0xRA5bBYMsFaL3BnqgiuiP/VeZ8x20Ne6tAeny7KuY3TtdmK/TUtzPPyHOb2hPGc+fgUeCnktnupdUXv0/Q/eeVo/yOdymspk235IgZ/8nQJ8dvvKif6XmOCej1N47OMfZijkHuWOpAvyDZHzml7g23z+NIvmdLwrgjC0239oOXcBJ5HFoIY8sXgx+sW5e7OxoCu2LszKAT/5UxvyJaztBZC6C+t53m+MMvIp45pGFOTcTyRvDWQ/xkvnn+/fgs7yNttLGIz3gZEz0D7L16sYRqwNNUQmD X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:nebula.arm.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230028)(4636009)(39860400002)(136003)(346002)(396003)(376002)(451199021)(36840700001)(46966006)(40470700004)(6666004)(478600001)(8676002)(8936002)(36756003)(5660300002)(7696005)(70206006)(70586007)(6916009)(40460700003)(316002)(41300700001)(40480700001)(356005)(81166007)(47076005)(186003)(44832011)(30864003)(1076003)(2616005)(26005)(336012)(426003)(83380400001)(82310400005)(86362001)(36860700001)(2906002)(82740400003)(36900700001); DIR:OUT; SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV2PR08MB9160 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DBAEUR03FT033.eop-EUR03.prod.protection.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 79b99f41-7332-4456-348f-08db7970bf3e X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: kqrMijON0jNGv80x1PrI0Ow+tWfMWdcMs/ldfmWw1LhXXbE9iytDqjjsGDes1AjrGv6epaZy2IOhxS6wNQZeTar9esLSxfDEhNjKTGQ+6w9WWRAJViG5obnqfHU4tz8yIHoZK7aNb2gicED3bbWG9f+kvWtQlqrRVuUXRjt376NpB4orTd0tiPnc1kN0JkprAGd0vLkMuiXcOSwlOIDQr9+XpTjsCMQj1ql7W1v4z+r+8M4BbhkTpVvedXdH4av/N8fnvmM5lbL9uN+85GhHSeK85EPBSFTfgh3FPQ+89TCeZEDPe8EPF7ZgwzFJGaAUUgfyGQiZtcq8AYSeGCzq/s03tUbq+VOETvGQc0TlASzi8MphV3fuxph7ODKzS350dQ3jPkRfPfneO9ITCtoligvl2qmnpKPiF4mRJfRhq7/D4lrrMdwmyX/fBzd8RpGodsAc1qPFlxymS8X+Lj3ss2406fZtSxSCu9JNsdyWmskY5/2467VoB//AyssnbrkyyydgMdATYVjhOdUMxGQ1s98zrgeFfC/aZXhPRSa7cU26MipuvuJ3MpAfGg8ByxNK7H4GUrob2Jk2kIpW8T8z0SMntrg+7gbIszG+zrlrXV21liWU0wpCBTO3sAUzuCvtvXyrjp0DwVHGDMmuY1/10uX8DGCegxNlMp0DnY68Kh6UXsb/ENOYzr0qt7Sgpb74r5Vys3KrmFmTZ5HA0kc7X6YvsmLSLz66Lj3AOGi1XyI= X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230028)(4636009)(39860400002)(396003)(136003)(376002)(346002)(451199021)(40470700004)(36840700001)(46966006)(44832011)(5660300002)(6916009)(478600001)(70206006)(316002)(36756003)(70586007)(8936002)(8676002)(2906002)(6666004)(26005)(40460700003)(36860700001)(30864003)(41300700001)(82310400005)(7696005)(186003)(40480700001)(426003)(336012)(47076005)(1076003)(86362001)(82740400003)(81166007)(83380400001)(2616005); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jun 2023 13:49:05.5888 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c683cf2c-3174-45bd-76cf-08db7970c543 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT033.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB8565 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_NUMSUBJECT, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Luis Machado via Gdb-patches From: Luis Machado Reply-To: Luis Machado Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org Sender: "Gdb-patches" Reusing the SME tests, this patch introduces additional tests to exercise reading/writing ZT0, availability of the register set, signal context reading for ZT0 and also core file generation. --- gdb/testsuite/gdb.arch/aarch64-sme-core.c | 32 +++++++++++++- .../gdb.arch/aarch64-sme-core.exp.tcl | 2 +- .../aarch64-sme-regs-available.exp.tcl | 17 +++++++ .../gdb.arch/aarch64-sme-regs-sigframe.c | 32 +++++++++++++- .../aarch64-sme-regs-sigframe.exp.tcl | 13 +++++- .../aarch64-sme-regs-unavailable.exp.tcl | 12 +++++ gdb/testsuite/gdb.arch/aarch64-sme-sanity.c | 32 +++++++++++++- gdb/testsuite/lib/aarch64.exp | 44 +++++++++++++++++++ 8 files changed, 176 insertions(+), 8 deletions(-) diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-core.c b/gdb/testsuite/gdb.arch/aarch64-sme-core.c index d71d18ebd3b..fcb14670e0d 100644 --- a/gdb/testsuite/gdb.arch/aarch64-sme-core.c +++ b/gdb/testsuite/gdb.arch/aarch64-sme-core.c @@ -35,6 +35,11 @@ #define HWCAP2_SME (1 << 23) #endif +#ifndef HWCAP2_SME2 +#define HWCAP2_SME2 (1UL << 37) +#define HWCAP2_SME2P1 (1UL << 38) +#endif + #ifndef PR_SVE_SET_VL #define PR_SVE_SET_VL 50 #define PR_SVE_GET_VL 51 @@ -145,6 +150,27 @@ initialize_za_state () __asm __volatile ("bne loop"); } +static void +initialize_zt_state () +{ + unsigned long hwcap2 = getauxval (AT_HWCAP2); + + if (!(hwcap2 & HWCAP2_SME2) && !(hwcap2 & HWCAP2_SME2P1)) + return; + + char buffer[64]; + + for (int i = 0; i < 64; i++) + buffer[i] = 0xff; + + __asm __volatile ("mov x0, %0\n\t" \ + : : "r" (buffer)); + + /* Initialize ZT0. */ + /* ldr zt0, x0 */ + __asm __volatile (".word 0xe11f8000"); +} + static void initialize_tpidr2 () { @@ -273,8 +299,8 @@ static int set_svl_size (int new_svl) 0 - FPSIMD 1 - SVE 2 - SSVE - 3 - ZA - 4 - ZA and SSVE. */ + 3 - ZA (+ SME2 ZT0) + 4 - ZA and SSVE (+ SME2 ZT0). */ void enable_states (int state) { @@ -295,6 +321,7 @@ void enable_states (int state) { enable_za (); initialize_za_state (); + initialize_zt_state (); } else if (state == 4) { @@ -302,6 +329,7 @@ void enable_states (int state) enable_sm (); initialize_sve_state (); initialize_za_state (); + initialize_zt_state (); } return; diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-core.exp.tcl b/gdb/testsuite/gdb.arch/aarch64-sme-core.exp.tcl index ed229982d7c..f4435a172f1 100644 --- a/gdb/testsuite/gdb.arch/aarch64-sme-core.exp.tcl +++ b/gdb/testsuite/gdb.arch/aarch64-sme-core.exp.tcl @@ -13,7 +13,7 @@ # You should have received a copy of the GNU General Public License # along with this program. If not, see . # -# Exercise core file reading/writing in the presence of SME support. +# Exercise core file reading/writing in the presence of SME and SME2 support. # This test exercises GDB's dumping/loading capability for Linux # Kernel core files and for gcore core files. diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-regs-available.exp.tcl b/gdb/testsuite/gdb.arch/aarch64-sme-regs-available.exp.tcl index 635588777ec..c76d2f68933 100644 --- a/gdb/testsuite/gdb.arch/aarch64-sme-regs-available.exp.tcl +++ b/gdb/testsuite/gdb.arch/aarch64-sme-regs-available.exp.tcl @@ -14,6 +14,7 @@ # along with this program. If not, see . # Exercise reading/writing ZA registers when there is ZA state. +# Exercise reading/writing to ZT0 when there is ZA state available. load_lib aarch64.exp @@ -119,6 +120,22 @@ proc check_regs { mode vl svl } { set last_slice [expr ($last_slice / 2)] set num_elements [expr $num_elements / 2] } + + # Exercise reading/writing from/to SME2 registers. + if [is_sme2_available] { + # The target supports SME2. + set zt_size 64 + gdb_test "print sizeof \$zt0" " = $zt_size" + + # Initially, when ZA is activated, ZT0 will be all zeroes. + set zt_pattern [string_to_regexp [1d_array_value_pattern 0 $zt_size]] + gdb_test "print \$zt0" " = $zt_pattern" "validate zeroed zt0" + + # Validate that writing to ZT0 does the right thing. + initialize_1d_array "\$zt0" 255 $zt_size + set zt_pattern [string_to_regexp [1d_array_value_pattern 255 $zt_size]] + gdb_test "print \$zt0" " = $zt_pattern" "read back from zt0" + } } # diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe.c b/gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe.c index 9bc3e9c16fc..8f0827cf83a 100644 --- a/gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe.c +++ b/gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe.c @@ -34,6 +34,11 @@ #define HWCAP2_SME (1 << 23) #endif +#ifndef HWCAP2_SME2 +#define HWCAP2_SME2 (1UL << 37) +#define HWCAP2_SME2P1 (1UL << 38) +#endif + #ifndef PR_SVE_SET_VL #define PR_SVE_SET_VL 50 #define PR_SVE_GET_VL 51 @@ -152,6 +157,27 @@ initialize_za_state () __asm __volatile ("bne loop"); } +static void +initialize_zt_state () +{ + unsigned long hwcap2 = getauxval (AT_HWCAP2); + + if (!(hwcap2 & HWCAP2_SME2) && !(hwcap2 & HWCAP2_SME2P1)) + return; + + char buffer[64]; + + for (int i = 0; i < 64; i++) + buffer[i] = 0xff; + + __asm __volatile ("mov x0, %0\n\t" \ + : : "r" (buffer)); + + /* Initialize ZT0. */ + /* ldr zt0, x0 */ + __asm __volatile (".word 0xe11f8000"); +} + static void initialize_sve_state () { @@ -271,8 +297,8 @@ static int set_svl_size (int new_svl) 0 - FPSIMD 1 - SVE 2 - SSVE - 3 - ZA - 4 - ZA and SSVE. */ + 3 - ZA (+ SME2 ZT0) + 4 - ZA and SSVE (+ SME2 ZT0). */ void enable_states (int state) { @@ -293,6 +319,7 @@ void enable_states (int state) { enable_za (); initialize_za_state (); + initialize_zt_state (); } else if (state == 4) { @@ -300,6 +327,7 @@ void enable_states (int state) enable_sm (); initialize_sve_state (); initialize_za_state (); + initialize_zt_state (); } return; diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe.exp.tcl b/gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe.exp.tcl index 0a9eae7dc5e..a1553deaab3 100644 --- a/gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe.exp.tcl +++ b/gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe.exp.tcl @@ -90,10 +90,12 @@ proc test_sme_registers_sigframe { id_start id_end } { # Check the value of SVCR. gdb_test "print \$svcr" [get_svcr_value $state] "svcr before signal" - # Handle SME ZA initialization and state. + # Handle SME ZA and SME2 initialization and state. set byte 0 + set sme2_byte 0 if { $state == "za" || $state == "za_ssve" } { set byte 170 + set sme2_byte 255 } # Set the expected ZA pattern. @@ -160,6 +162,15 @@ proc test_sme_registers_sigframe { id_start id_end } { # Check the value of TPIDR2 in the signal frame. gdb_test "print/x \$tpidr2" " = 0x102030405060708" "tpidr2 contents from signal frame" + + # Check the value of SME2 ZT0 in the signal frame. + if [is_sme2_available] { + # The target supports SME2. + set zt_size 64 + gdb_test "print sizeof \$zt0" " = $zt_size" + set zt_pattern [string_to_regexp [1d_array_value_pattern $sme2_byte $zt_size]] + gdb_test "print \$zt0" " = $zt_pattern" "zt contents from signal frame" + } } } } diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable.exp.tcl b/gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable.exp.tcl index 69c70ae87b3..0f0045cb827 100644 --- a/gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable.exp.tcl +++ b/gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable.exp.tcl @@ -17,6 +17,7 @@ # - Printing ZA registers when there is no ZA state. # - Setting values of ZA registers when there is no ZA state. # - Validating ZA state is activated when we write to ZA registers. +# - Validate that reading ZT0 without an active ZA state works as expected. load_lib aarch64.exp @@ -89,6 +90,17 @@ proc_with_prefix check_regs { vl svl } { set expected_size [expr $expected_size / 2] set elements [expr ($elements / 2)] } + + # Exercise reading from SME2 registers. + if [is_sme2_available] { + # The target supports SME2. + set zt_size 64 + gdb_test "print sizeof \$zt0" " = $zt_size" + + # If ZA is not active, ZT0 will always be zero. + set zt_pattern [string_to_regexp [1d_array_value_pattern 0 $zt_size]] + gdb_test "print \$zt0" " = $zt_pattern" + } } # diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-sanity.c b/gdb/testsuite/gdb.arch/aarch64-sme-sanity.c index 694de0626d2..71b46b17855 100644 --- a/gdb/testsuite/gdb.arch/aarch64-sme-sanity.c +++ b/gdb/testsuite/gdb.arch/aarch64-sme-sanity.c @@ -33,6 +33,11 @@ #define HWCAP2_SME (1 << 23) #endif +#ifndef HWCAP2_SME2 +#define HWCAP2_SME2 (1UL << 37) +#define HWCAP2_SME2P1 (1UL << 38) +#endif + static void enable_za () { @@ -131,6 +136,27 @@ initialize_za_state () __asm __volatile ("bne loop"); } +static void +initialize_zt_state () +{ + unsigned long hwcap2 = getauxval (AT_HWCAP2); + + if (!(hwcap2 & HWCAP2_SME2) && !(hwcap2 & HWCAP2_SME2P1)) + return; + + char buffer[64]; + + for (int i = 0; i < 64; i++) + buffer[i] = 0xff; + + __asm __volatile ("mov x0, %0\n\t" \ + : : "r" (buffer)); + + /* Initialize ZT0. */ + /* ldr zt0, x0 */ + __asm __volatile (".word 0xe11f8000"); +} + static void initialize_sve_state () { @@ -190,8 +216,8 @@ initialize_sve_state () 0 - FPSIMD 1 - SVE 2 - SSVE - 3 - ZA - 4 - ZA and SSVE. */ + 3 - ZA (+ SME2 ZT0) + 4 - ZA and SSVE (+ SME2 ZT0). */ void enable_states (int state) { @@ -212,6 +238,7 @@ void enable_states (int state) { enable_za (); initialize_za_state (); + initialize_zt_state (); } else if (state == 4) { @@ -219,6 +246,7 @@ void enable_states (int state) enable_sm (); initialize_sve_state (); initialize_za_state (); + initialize_zt_state (); } return; diff --git a/gdb/testsuite/lib/aarch64.exp b/gdb/testsuite/lib/aarch64.exp index 031ffa68373..84189976663 100644 --- a/gdb/testsuite/lib/aarch64.exp +++ b/gdb/testsuite/lib/aarch64.exp @@ -319,6 +319,18 @@ proc check_sme_regs { byte state svl } { gdb_test "print \$za" $za_pattern } +# +# Validate the values of the SME2 registers. +# +proc check_sme2_regs { byte } { + # The size of the ZT registers should always be fixed to 64 bytes. + set zt_size 64 + gdb_test "print sizeof \$zt0" " = $zt_size" + # Check that we have the expected pattern of bytes for the ZT registers. + set zt_pattern [string_to_regexp [1d_array_value_pattern $byte $zt_size]] + gdb_test "print \$zt0" $zt_pattern +} + # # With register STATE, vector length VL and streaming vector length SVL, # run some register state checks to make sure the values are the expected @@ -333,6 +345,9 @@ proc check_state { state vl svl } { # # The SME (ZA) register is initialized with a value of 0xaa (170) for # each byte. + # + # The SME2 (ZT) registers are initialized with a value of 0xff (255) for + # each byte. # Check VG to make sure it is correct set expected_vg [expr $vl / 8] @@ -367,6 +382,35 @@ proc check_state { state vl svl } { check_sve_regs $sve_byte $state $vl $svl # Check SME registers check_sme_regs 170 $state $svl + + # Check SME2 registers + if [is_sme2_available] { + # The SME2 ZT0 register will always be zero, except when ZA is active. + set sme2_byte 0 + if {$state == "za" || $state == "za_ssve"} { + set sme2_byte 255 + } + + # The target supports SME2, so check the ZT register values. + check_sme2_regs $sme2_byte + } } +# +# Return 1 if SME2 is available (meaning the ZT0 register exists). +# Return 0 otherwise. +# +proc is_sme2_available { } { + # Does the ZT0 register exist? + gdb_test_multiple "print \$zt0" "" { + -re " = void.*${::gdb_prompt} $" { + # SME2 is not available. + return 0 + } + -re " = {.*}\r\n${::gdb_prompt} $" { + # SME2 is available. + return 1 + } + } +}