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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230028)(4636009)(39860400002)(346002)(376002)(396003)(136003)(451199021)(40470700004)(36840700001)(46966006)(86362001)(36756003)(316002)(70206006)(6916009)(70586007)(478600001)(40480700001)(6666004)(82310400005)(8936002)(8676002)(5660300002)(41300700001)(2906002)(44832011)(81166007)(82740400003)(7696005)(186003)(336012)(426003)(2616005)(26005)(1076003)(36860700001)(47076005)(83380400001)(40460700003); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2023 10:25:22.0320 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6ddce4ef-8bb2-4c37-c20f-08db58535a24 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT055.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV2PR08MB8004 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Luis Machado via Gdb-patches From: Luis Machado Reply-To: Luis Machado Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org Sender: "Gdb-patches" I noticed we don't handle register reads/writes in the best way for native AArch64 Linux. Some registers are fetched/stored even if upper level code told us to fetch a particular register number. Fix this by being more strict about which registers we touch when reading/writing them in the native AArch64 Linux layer. There should be no user-visible changes due to this patch. Regression-tested on aarch64-linux Ubuntu 22.04/20.04. --- gdb/aarch64-linux-nat.c | 60 ++++++++++++++++++++++------------------- 1 file changed, 33 insertions(+), 27 deletions(-) diff --git a/gdb/aarch64-linux-nat.c b/gdb/aarch64-linux-nat.c index ecb2eeb9540..62656a7347b 100644 --- a/gdb/aarch64-linux-nat.c +++ b/gdb/aarch64-linux-nat.c @@ -504,6 +504,7 @@ aarch64_fetch_registers (struct regcache *regcache, int regno) aarch64_gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); + /* Do we need to fetch all registers? */ if (regno == -1) { fetch_gregs_from_thread (regcache); @@ -521,28 +522,28 @@ aarch64_fetch_registers (struct regcache *regcache, int regno) if (tdep->has_tls ()) fetch_tlsregs_from_thread (regcache); } + /* General purpose register? */ else if (regno < AARCH64_V0_REGNUM) fetch_gregs_from_thread (regcache); - else if (tdep->has_sve ()) + /* SVE register? */ + else if (tdep->has_sve () && regno <= AARCH64_SVE_VG_REGNUM) fetch_sveregs_from_thread (regcache); - else + /* FPSIMD register? */ + else if (regno < AARCH64_FPCR_REGNUM) fetch_fpregs_from_thread (regcache); - - if (tdep->has_pauth ()) - { - if (regno == AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base) - || regno == AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base)) - fetch_pauth_masks_from_thread (regcache); - } - - /* Fetch individual MTE registers. */ - if (tdep->has_mte () - && (regno == tdep->mte_reg_base)) + /* PAuth register? */ + else if (tdep->has_pauth () + && (regno == AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base) + || regno == AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base))) + fetch_pauth_masks_from_thread (regcache); + /* MTE register? */ + else if (tdep->has_mte () + && (regno == tdep->mte_reg_base)) fetch_mteregs_from_thread (regcache); - - if (tdep->has_tls () - && regno >= tdep->tls_regnum_base - && regno < tdep->tls_regnum_base + tdep->tls_register_count) + /* TLS register? */ + else if (tdep->has_tls () + && regno >= tdep->tls_regnum_base + && regno < tdep->tls_regnum_base + tdep->tls_register_count) fetch_tlsregs_from_thread (regcache); } @@ -592,6 +593,7 @@ aarch64_store_registers (struct regcache *regcache, int regno) aarch64_gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); + /* Do we need to store all registers? */ if (regno == -1) { store_gregs_to_thread (regcache); @@ -606,22 +608,26 @@ aarch64_store_registers (struct regcache *regcache, int regno) if (tdep->has_tls ()) store_tlsregs_to_thread (regcache); } + /* General purpose register? */ else if (regno < AARCH64_V0_REGNUM) store_gregs_to_thread (regcache); - else if (tdep->has_sve ()) + /* SVE register? */ + else if (tdep->has_sve () && regno <= AARCH64_SVE_VG_REGNUM) store_sveregs_to_thread (regcache); - else + /* FPSIMD register? */ + else if (regno < AARCH64_FPCR_REGNUM) store_fpregs_to_thread (regcache); - - /* Store MTE registers. */ - if (tdep->has_mte () - && (regno == tdep->mte_reg_base)) + /* MTE register? */ + else if (tdep->has_mte () + && (regno == tdep->mte_reg_base)) store_mteregs_to_thread (regcache); - - if (tdep->has_tls () - && regno >= tdep->tls_regnum_base - && regno < tdep->tls_regnum_base + tdep->tls_register_count) + /* TLS register? */ + else if (tdep->has_tls () + && regno >= tdep->tls_regnum_base + && regno < tdep->tls_regnum_base + tdep->tls_register_count) store_tlsregs_to_thread (regcache); + + /* PAuth registers are read-only. */ } /* A version of the "store_registers" target_ops method used when running