[v3,17/17,gdb/docs] sme: Document SME registers and features
Commit Message
Updates since v2:
- More adjustments based on reviews.
- Fixed incorrect number of tile pseudo-registers.
- Fixed naming of tile slice pseudo-registers.
- More detail about SME and how gdb implements it.
- Attempted to clarify the text a bit more.
Updates since v1:
- Made SME text more thorough.
- Adjusted text based on upstream reviews.
- Fixed documentation errors (missing itemization for SME registers).
Provide documentation for the SME feature and other information that
should be useful for users that need to debug a SME-capable target.
---
gdb/NEWS | 11 ++
gdb/doc/gdb.texinfo | 249 ++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 260 insertions(+)
Comments
> From: Luis Machado <luis.machado@arm.com>
> Date: Mon, 17 Apr 2023 18:19:45 +0100
>
> Provide documentation for the SME feature and other information that
> should be useful for users that need to debug a SME-capable target.
> ---
> gdb/NEWS | 11 ++
> gdb/doc/gdb.texinfo | 249 ++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 260 insertions(+)
Thanks.
> diff --git a/gdb/NEWS b/gdb/NEWS
> index 54b5da21245..e3ce7d7e881 100644
> --- a/gdb/NEWS
> +++ b/gdb/NEWS
> @@ -3,6 +3,17 @@
>
> *** Changes since GDB 13
>
> +* GDB now supports the AArch64 Scalable Matrix Extension (SME), which includes
> + a new matrix register named ZA, a new thread register TPIDR2 and a new vector
> + length register SVG (streaming vector granule). GDB also supports tracking
> + ZA state across signal frames.
> +
> + Some features are still under development or are dependent on ABI specs that
> + are still in alpha stage. For example, manual function calls with ZA state
> + don't have any special handling, and tracking of SVG changes based on
> + DWARF information is still not implemented, but there are plans to do so in
> + the future.
> +
> * The AArch64 'org.gnu.gdb.aarch64.pauth' Pointer Authentication feature string
> has been deprecated in favor of the 'org.gnu.gdb.aarch64.pauth_v2' feature
> string.
This part is OK.
> +For SVE, the following definitions are used throughout @value{GDBN}'s source
> +code and in this document:
> +
> +@itemize
> +
> +@item
> +@anchor{VL}
> +@cindex VL
> +@code{VL}: The vector length, in bytes. It defines the size of each @code{Z}
> +register.
> +
> +@item
> +@anchor{VQ}
> +@cindex VQ
> +@code{VQ}: The number of 128 bit units in @code{VL}. This is mostly used
> +internally by @value{GDBN} and the Linux Kernel.
> +
> +@item
> +@anchor{VG}
> +@cindex VG
> +@code{VG}: The number of 64 bit units in @code{VL}. This is mostly used
> +internally by @value{GDBN} and the Linux Kernel.
I thought we agreed to use @var{vl}, @var{vq}, etc., instead of
@code{VL} etc.? These are meta-syntactic parameters, they stand for
something else, not literally for themselves, so @var is more
appropriate.
Also, you place @cindex between @item and the text of the @item -- did
you verify that typing "i VQ" in an Info reader goes to the beginning
of the item's line? I think @cindex should be before @item.
> +Similarly to SVE, where the size of each @code{Z} register is directly related
> +to the vector length (@code{VL} for short), the @acronym{SME} @code{ZA} matrix
> +register's size is directly related to the streaming vector length
Elsewhere you use @code{za}, lower-case, for the register. Please be
consistent in the capitalization of the register names.
> +(@code{SVL} for short). @xref{VL} @xref{SVL}
^^
Two spaces there.
> +@item
> +@anchor{SVL}
> +@cindex SVL
> +@code{SVL}: The streaming vector length, in bytes. It defines the size of each
> +dimension of the 2-dimensional square @code{ZA} matrix. The total size of
> +@code{ZA} is therefore @code{@var{SVL}x@var{SVL}}.
> +
> +When streaming mode is enabled, it defines the size of the @acronym{SVE}
> +registers as well.
> +
> +@item
> +@anchor{SVQ}
> +@cindex SVQ
> +@code{SVQ}: The number of 128 bit units in @code{SVL}. This is mostly used
> +internally by @value{GDBN} and the Linux Kernel.
> +
> +@item
> +@anchor{SVG}
> +@cindex SVG
> +@code{SVG}: The number of 64 bit units in @code{SVL}. This is mostly used
> +internally by @value{GDBN} and the Linux Kernel.
Likewise here: I thought we agreed on using @var{svl} etc., not
@code{SVL}.
> +The @code{za} register is a 2-dimensional square @code{@var{SVL}x@var{SVL}}
And here you actually use @var (which is correct), but with an
upper-case argument, which is sub-optimal. The argument of @var
should be in lower-case.
> +@item
> +@samp{za} is a register represented by a vector of @code{SVL} x @code{SVL}
^^^^^^^^^^^^^^^^^^^^^^^
This should use @var, not @code. Also, I'd remove the whitespace
around "x".
Reviewed-By: Eli Zaretskii <eliz@gnu.org>
On 4/22/23 10:21, Eli Zaretskii wrote:
>> From: Luis Machado <luis.machado@arm.com>
>> Date: Mon, 17 Apr 2023 18:19:45 +0100
>>
>> Provide documentation for the SME feature and other information that
>> should be useful for users that need to debug a SME-capable target.
>> ---
>> gdb/NEWS | 11 ++
>> gdb/doc/gdb.texinfo | 249 ++++++++++++++++++++++++++++++++++++++++++++
>> 2 files changed, 260 insertions(+)
>
> Thanks.
>
>> diff --git a/gdb/NEWS b/gdb/NEWS
>> index 54b5da21245..e3ce7d7e881 100644
>> --- a/gdb/NEWS
>> +++ b/gdb/NEWS
>> @@ -3,6 +3,17 @@
>>
>> *** Changes since GDB 13
>>
>> +* GDB now supports the AArch64 Scalable Matrix Extension (SME), which includes
>> + a new matrix register named ZA, a new thread register TPIDR2 and a new vector
>> + length register SVG (streaming vector granule). GDB also supports tracking
>> + ZA state across signal frames.
>> +
>> + Some features are still under development or are dependent on ABI specs that
>> + are still in alpha stage. For example, manual function calls with ZA state
>> + don't have any special handling, and tracking of SVG changes based on
>> + DWARF information is still not implemented, but there are plans to do so in
>> + the future.
>> +
>> * The AArch64 'org.gnu.gdb.aarch64.pauth' Pointer Authentication feature string
>> has been deprecated in favor of the 'org.gnu.gdb.aarch64.pauth_v2' feature
>> string.
>
> This part is OK.
>
>> +For SVE, the following definitions are used throughout @value{GDBN}'s source
>> +code and in this document:
>> +
>> +@itemize
>> +
>> +@item
>> +@anchor{VL}
>> +@cindex VL
>> +@code{VL}: The vector length, in bytes. It defines the size of each @code{Z}
>> +register.
>> +
>> +@item
>> +@anchor{VQ}
>> +@cindex VQ
>> +@code{VQ}: The number of 128 bit units in @code{VL}. This is mostly used
>> +internally by @value{GDBN} and the Linux Kernel.
>> +
>> +@item
>> +@anchor{VG}
>> +@cindex VG
>> +@code{VG}: The number of 64 bit units in @code{VL}. This is mostly used
>> +internally by @value{GDBN} and the Linux Kernel.
>
> I thought we agreed to use @var{vl}, @var{vq}, etc., instead of
> @code{VL} etc.? These are meta-syntactic parameters, they stand for
> something else, not literally for themselves, so @var is more
> appropriate.
Ok. That wasn't completely clear to me. I've made the change now.
>
> Also, you place @cindex between @item and the text of the @item -- did
> you verify that typing "i VQ" in an Info reader goes to the beginning
> of the item's line? I think @cindex should be before @item.
You're right. Fixed and verified now.
>
>> +Similarly to SVE, where the size of each @code{Z} register is directly related
>> +to the vector length (@code{VL} for short), the @acronym{SME} @code{ZA} matrix
>> +register's size is directly related to the streaming vector length
>
> Elsewhere you use @code{za}, lower-case, for the register. Please be
> consistent in the capitalization of the register names.
>
All the uses of za should now be lower-case.
>> +(@code{SVL} for short). @xref{VL} @xref{SVL}
> ^^
> Two spaces there.
>
Fixed.
>> +@item
>> +@anchor{SVL}
>> +@cindex SVL
>> +@code{SVL}: The streaming vector length, in bytes. It defines the size of each
>> +dimension of the 2-dimensional square @code{ZA} matrix. The total size of
>> +@code{ZA} is therefore @code{@var{SVL}x@var{SVL}}.
>> +
>> +When streaming mode is enabled, it defines the size of the @acronym{SVE}
>> +registers as well.
>> +
>> +@item
>> +@anchor{SVQ}
>> +@cindex SVQ
>> +@code{SVQ}: The number of 128 bit units in @code{SVL}. This is mostly used
>> +internally by @value{GDBN} and the Linux Kernel.
>> +
>> +@item
>> +@anchor{SVG}
>> +@cindex SVG
>> +@code{SVG}: The number of 64 bit units in @code{SVL}. This is mostly used
>> +internally by @value{GDBN} and the Linux Kernel.
>
> Likewise here: I thought we agreed on using @var{svl} etc., not
> @code{SVL}.
>
Fixed now.
>> +The @code{za} register is a 2-dimensional square @code{@var{SVL}x@var{SVL}}
>
> And here you actually use @var (which is correct), but with an
> upper-case argument, which is sub-optimal. The argument of @var
> should be in lower-case.
>
Fixed.
>> +@item
>> +@samp{za} is a register represented by a vector of @code{SVL} x @code{SVL}
> ^^^^^^^^^^^^^^^^^^^^^^^
> This should use @var, not @code. Also, I'd remove the whitespace
> around "x".
Fixed. But I used spaces between "x" and the two @var entries because it gets rendered as a single
block of characters like svlxsvl.
Using @math{x} doesn't look too nice. Suggestions?
>
> Reviewed-By: Eli Zaretskii <eliz@gnu.org>
> Date: Wed, 26 Apr 2023 16:00:44 +0100
> Cc: gdb-patches@sourceware.org
> From: Luis Machado <luis.machado@arm.com>
>
> >> +@item
> >> +@samp{za} is a register represented by a vector of @code{SVL} x @code{SVL}
> > ^^^^^^^^^^^^^^^^^^^^^^^
> > This should use @var, not @code. Also, I'd remove the whitespace
> > around "x".
>
> Fixed. But I used spaces between "x" and the two @var entries because it gets rendered as a single
> block of characters like svlxsvl.
That doesn't seem possible, since @var produces a different typeface:
slanted in the printed version and CAPS in the Info versions. Where
did you see svlxsvl?
> Date: Thu, 27 Apr 2023 09:35:15 +0100
> Cc: gdb-patches@sourceware.org
> From: Luis Machado <luis.machado@arm.com>
>
> >>> This should use @var, not @code. Also, I'd remove the whitespace
> >>> around "x".
> >>
> >> Fixed. But I used spaces between "x" and the two @var entries because it gets rendered as a single
> >> block of characters like svlxsvl.
> >
> > That doesn't seem possible, since @var produces a different typeface:
> > slanted in the printed version and CAPS in the Info versions. Where
> > did you see svlxsvl?
>
> In the PDF. I mean, it is slanted with the use of @var{}, but not that noticeable.
>
> See the attached pdf. I also attached the info file.
Then maybe use "@var{svl} by @var{svl}"?
> I noticed the info file capitalizes @var{}, which might not be ideal?
That cannot be helped. It isn't ideal, indeed, but given that Info
manuals must be displayed on plain-text terminals, there's not a lot
Texinfo can play with.
On 4/27/23 10:10, Eli Zaretskii wrote:
>> Date: Thu, 27 Apr 2023 09:35:15 +0100
>> Cc: gdb-patches@sourceware.org
>> From: Luis Machado <luis.machado@arm.com>
>>
>>>>> This should use @var, not @code. Also, I'd remove the whitespace
>>>>> around "x".
>>>>
>>>> Fixed. But I used spaces between "x" and the two @var entries because it gets rendered as a single
>>>> block of characters like svlxsvl.
>>>
>>> That doesn't seem possible, since @var produces a different typeface:
>>> slanted in the printed version and CAPS in the Info versions. Where
>>> did you see svlxsvl?
>>
>> In the PDF. I mean, it is slanted with the use of @var{}, but not that noticeable.
>>
>> See the attached pdf. I also attached the info file.
>
> Then maybe use "@var{svl} by @var{svl}"?
>
I'll do that then.
>> I noticed the info file capitalizes @var{}, which might not be ideal?
>
> That cannot be helped. It isn't ideal, indeed, but given that Info
> manuals must be displayed on plain-text terminals, there's not a lot
> Texinfo can play with.
Fair enough.
Thanks for the review.
@@ -3,6 +3,17 @@
*** Changes since GDB 13
+* GDB now supports the AArch64 Scalable Matrix Extension (SME), which includes
+ a new matrix register named ZA, a new thread register TPIDR2 and a new vector
+ length register SVG (streaming vector granule). GDB also supports tracking
+ ZA state across signal frames.
+
+ Some features are still under development or are dependent on ABI specs that
+ are still in alpha stage. For example, manual function calls with ZA state
+ don't have any special handling, and tracking of SVG changes based on
+ DWARF information is still not implemented, but there are plans to do so in
+ the future.
+
* The AArch64 'org.gnu.gdb.aarch64.pauth' Pointer Authentication feature string
has been deprecated in favor of the 'org.gnu.gdb.aarch64.pauth_v2' feature
string.
@@ -26045,6 +26045,224 @@ but the lengths of the @code{z} and @code{p} registers will not change. This
is a known limitation of @value{GDBN} and does not affect the execution of the
target process.
+For SVE, the following definitions are used throughout @value{GDBN}'s source
+code and in this document:
+
+@itemize
+
+@item
+@anchor{VL}
+@cindex VL
+@code{VL}: The vector length, in bytes. It defines the size of each @code{Z}
+register.
+
+@item
+@anchor{VQ}
+@cindex VQ
+@code{VQ}: The number of 128 bit units in @code{VL}. This is mostly used
+internally by @value{GDBN} and the Linux Kernel.
+
+@item
+@anchor{VG}
+@cindex VG
+@code{VG}: The number of 64 bit units in @code{VL}. This is mostly used
+internally by @value{GDBN} and the Linux Kernel.
+
+@end itemize
+
+@subsubsection AArch64 SME.
+@anchor{AArch64 SME}
+@cindex SME
+@cindex AArch64 SME
+@cindex Scalable Matrix Extension
+
+The Scalable Matrix Extension (@url{https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/scalable-matrix-extension-armv9-a-architecture, @acronym{SME}})
+is an AArch64 architecture extension that expands on the concept of the
+Scalable Vector Extension (@url{https://developer.arm.com/documentation/101726/4-0/Learn-about-the-Scalable-Vector-Extension--SVE-/What-is-the-Scalable-Vector-Extension-, @acronym{SVE}})
+by providing a 2-dimensional register @code{ZA}, which is a square
+matrix of variable size, just like SVE provides a group of vector registers of
+variable size.
+
+Similarly to SVE, where the size of each @code{Z} register is directly related
+to the vector length (@code{VL} for short), the @acronym{SME} @code{ZA} matrix
+register's size is directly related to the streaming vector length
+(@code{SVL} for short). @xref{VL} @xref{SVL}
+
+The @code{ZA} matrix state can be either active or inactive, if it is not in
+use.
+
+@acronym{SME} also introduces a new execution mode called streaming
+@acronym{SVE} mode (streaming mode for short). When streaming mode is
+enabled, the program supports execution of @acronym{SVE2} instructions and the
+@acronym{SVE} registers will have vector length @code{SVL}. When streaming
+mode is disabled, the SVE registers have vector length @code{VL}.
+
+For more information about @acronym{SME} and @acronym{SVE}, please refer to
+official @url{https://developer.arm.com/documentation/ddi0487/latest,
+architecture documentation}.
+
+The following definitions are used throughout @value{GDBN}'s source code and
+in this document:
+
+@itemize
+
+@item
+@anchor{SVL}
+@cindex SVL
+@code{SVL}: The streaming vector length, in bytes. It defines the size of each
+dimension of the 2-dimensional square @code{ZA} matrix. The total size of
+@code{ZA} is therefore @code{@var{SVL}x@var{SVL}}.
+
+When streaming mode is enabled, it defines the size of the @acronym{SVE}
+registers as well.
+
+@item
+@anchor{SVQ}
+@cindex SVQ
+@code{SVQ}: The number of 128 bit units in @code{SVL}. This is mostly used
+internally by @value{GDBN} and the Linux Kernel.
+
+@item
+@anchor{SVG}
+@cindex SVG
+@code{SVG}: The number of 64 bit units in @code{SVL}. This is mostly used
+internally by @value{GDBN} and the Linux Kernel.
+
+@end itemize
+
+When @value{GDBN} is debugging the AArch64 architecture, if the Scalable Matrix
+Extension (@acronym{SME}) is present, then @value{GDBN} will make the @code{za}
+register available. @value{GDBN} will also make the @code{svg} register and
+@code{svcr} pseudo-register available.
+
+The @code{za} register is a 2-dimensional square @code{@var{SVL}x@var{SVL}}
+matrix of bytes. To simplify the representation and access to the @code{za}
+register in @value{GDBN}, it is defined as a vector of
+@code{@var{SVL}x@var{SVL}} bytes.
+
+If the user wants to index the @code{za} register as a matrix, it is possible
+to reference @code{za} as @code{za[@var{i}][@var{j}]}, where @var{i} is the
+row number and @var{j} is the column number.
+
+The @code{svg} register always contains the streaming vector granule
+(@code{SVG}) for the current thread. From @code{SVG} we can easily derive
+the @code{SVL} value.
+
+@anchor{aarch64 sme svcr}
+The @code{svcr} pseudo-register (streaming vector control register) is a status
+register that holds two state bits: @sc{sm} in bit 0 and @sc{za} in bit 1.
+
+If the @sc{sm} bit is 1, it means the current thread is in streaming
+mode, and the @acronym{SVE} registers will use @code{SVL} for their sizes. If
+the @sc{sm} bit is 0, the current thread is not in streaming mode, and the
+@acronym{SVE} registers will use @code{VG} for their sizes. @xref{VG}.
+
+If the @sc{za} bit is 1, it means the @code{ZA} state, and therefore the
+@code{za} register, is being used and has meaningful contents. If the
+@sc{za} bit is 0, the @code{ZA} state is unavailable and the contents of the
+@code{za} register are undefined.
+
+For convenience and simplicity, if the @sc{za} bit is 0, the @code{za}
+register and all of its pseudo-registers will read as zero.
+
+If @code{SVL} changes during the execution of a program, then the @code{za}
+register size and the bits in the @code{svcr} pseudo-register will be updated
+to reflect it.
+
+It is possible for users to change @code{SVL} during the execution of a
+program by modifying the @code{svg} register value.
+
+Whenever the @code{svg} register is modified with a new value, the
+following will be observed:
+
+@itemize
+
+@item The @sc{za} and @sc{sm} bits will be cleared in the @code{svcr}
+pseudo-register.
+
+@item The @code{za} register will have a new size and its state will be
+cleared, forcing its contents and the contents of all of its pseudo-registers
+back to zero.
+
+@item If the @sc{sm} bit was 1, the @acronym{SVE} registers will be reset to
+having their sizes based on @code{VL} as opposed to @code{SVL}. If the
+@sc{sm} bit was 0 prior to modifying the @code{svg} register, there will be no
+observable effect on the @acronym{SVE} registers.
+
+@end itemize
+
+The possible values for the @code{svg} register are 2, 4, 8, 16, 32. These
+numbers correspond to streaming vector length (@code{SVL}) values of 16
+bytes, 32 bytes, 64 bytes, 128 bytes and 256 bytes respectively.
+
+The minimum size of the @code{za} register is 16 x 16 (256) bytes, and the
+maximum size is 256 x 256 (65536) bytes. In streaming mode, with bit @sc{sm}
+set, the size of the @code{za} register is the size of all the SVE @code{z}
+registers combined.
+
+The @code{za} register can also be accessed using tiles and tile slices.
+
+Tile pseudo-registers are square, 2-dimensional sub-arrays of elements within
+the @code{za} register.
+
+There is a total of 31 @code{za} tile pseudo-registers. They are
+@code{za0b}, @code{za0h} through @code{za1h}, @code{zas0} through @code{zas3},
+@code{zad0} through @code{zad7} and @code{zaq0} through @code{zaq15}.
+
+Tile slice pseudo-registers are vectors of horizontally or vertically
+contiguous elements within the @code{za} register.
+
+The tile slice pseudo-registers have the following naming pattern:
+@code{za<@var{tile number}><@var{direction}><@var{qualifier}>
+<@var{slice number}>}.
+
+There are up to 16 tiles (0 ~ 15), the direction can be either @code{v}
+(vertical) or @code{h} (horizontal), the qualifiers can be @code{b} (byte),
+@code{h} (halfword), @code{s} (word), @code{d} (doubleword) and @code{q}
+(quadword) and there are up to 256 slices (0 ~ 255) depending on the value
+of @code{SVL}. The number of slices is the same as the value of @code{SVL}.
+
+The number of available tile slice pseudo-registers can be large. For a
+minimum @code{SVL} of 16 bytes, there are 5 (number of qualifiers) x
+2 (number of directions) x 16 (@code{SVL}) pseudo-registers. For the
+maximum @code{SVL} of 256 bytes, there are 5 x 2 x 256 pseudo-registers.
+
+When listing all the available registers, users will see the
+currently-available @code{za} pseudo-registers. Pseudo-registers that don't
+exist for a given @code{SVL} value will not be displayed.
+
+For more information on @acronym{SME} and its terminology, please refer to the
+@url{https://developer.arm.com/documentation/ddi0616/aa/,
+Arm Architecture Reference Manual Supplement}, The Scalable Matrix Extension
+(@acronym{SME}), for Armv9-A.
+
+Some features are still under development and rely on
+@url{https://github.com/ARM-software/acle/releases/latest, ACLE} and
+@url{https://github.com/ARM-software/abi-aa/blob/main/aapcs64/aapcs64.rst, ABI}
+definitions, so there are known limitations to the current @acronym{SME}
+support in @value{GDBN}.
+
+One such example is calling functions in the program being debugged by
+@value{GDBN}. Such calls are not @acronym{SME}-aware and thus don't take into
+account the @code{svcr} pseudo-register bits nor the @code{za} register
+contents. @xref{Calling}
+
+The @url{https://github.com/ARM-software/abi-aa/blob/main/aapcs64/aapcs64.rst#the-za-lazy-saving-scheme,
+lazy saving scheme} involving the @code{tpidr2} register is not yet supported
+by @value{GDBN}, though the @code{tpidr2} register is known and supported
+by @value{GDBN}.
+
+Lastly, an important limitation for @code{gdbserver} is its inability to
+communicate @code{SVL} changes to @value{GDBN}. This means @code{gdbserver},
+even though it is capable of adjusting its internal caches to reflect a change
+in the value of @code{SVL} mid-execution, will operate with a potentially
+different @code{SVL} value compared to @value{GDBN}. This can lead to
+@value{GDBN} showing incorrect values for the @code{za} register and
+incorrect values for SVE registers (when in streaming mode).
+
+This is the same limitation we have for the @acronym{SVE} registers, and there
+are plans to address this limitation going forward.
+
@subsubsection AArch64 Pointer Authentication.
@cindex AArch64 Pointer Authentication.
@anchor{AArch64 PAC}
@@ -48071,6 +48289,37 @@ This restriction may be lifted in the future.
Extra registers are allowed in this feature, but they will not affect
@value{GDBN}.
+@subsubsection AArch64 SME registers feature
+
+The @samp{org.gnu.gdb.aarch64.sme} feature is optional. If present,
+it should contain registers @samp{za}, @samp{svg} and @samp{svcr}.
+@xref{AArch64 SME}
+
+@itemize @minus
+
+@item
+@samp{za} is a register represented by a vector of @code{SVL} x @code{SVL}
+bytes. @xref{SVL}
+
+@item
+@samp{svg} is a 64-bit register containing the value of @code{SVG}. @xref{SVG}.
+
+@item
+@samp{svcr} is a 64-bit status pseudo-register with two valid bits. Bit 0
+(@sc{sm}) shows whether the streaming @acronym{SVE} mode is enabled or disabled.
+Bit 1 (@sc{za}) shows whether the @code{za} register state is active (in use) or
+not.
+@xref{aarch64 sme svcr}
+
+The rest of the unused bits of the @samp{svcr} pseudo-register is undefined
+and reserved. Such bits should not be used and may be defined by future
+extensions of the architecture.
+
+@end itemize
+
+Extra registers are allowed in this feature, but they will not affect
+@value{GDBN}.
+
@node ARC Features
@subsection ARC Features
@cindex target descriptions, ARC Features