From patchwork Fri Dec 23 06:07:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Frysinger X-Patchwork-Id: 62344 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1BEEA38493F7 for ; Fri, 23 Dec 2022 06:10:28 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 1BEEA38493F7 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1671775828; bh=4JBwucZj7G0tvgrFDwGPGMMJkEAzoi4parg9NeBybYA=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=WiaXm0+unoG3hJO4qNQuqABzrquspbSagM+y/pYLuIUQ4XSjiFR+pne4eorlKkSW+ MH8XRa0LwgC6qUxDGjlKwWQnoidCK+AxXTyddGxDzCTQGnSdCAmNJrEOuFt2mOIM9b 5w6XXlNPDRBv+tj/GlICZSa/553CH1/2lQnJXJ4U= X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from smtp.gentoo.org (smtp.gentoo.org [IPv6:2001:470:ea4a:1:5054:ff:fec7:86e4]) by sourceware.org (Postfix) with ESMTP id 0BC7D384E7AD for ; Fri, 23 Dec 2022 06:07:53 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 0BC7D384E7AD Received: by smtp.gentoo.org (Postfix, from userid 559) id B69F53411D4; Fri, 23 Dec 2022 06:07:52 +0000 (UTC) To: gdb-patches@sourceware.org Subject: [PATCH 16/20] sim: mcore: move arch-specific settings to internal header Date: Fri, 23 Dec 2022 01:07:09 -0500 Message-Id: <20221223060713.28821-17-vapier@gentoo.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221223060713.28821-1-vapier@gentoo.org> References: <20221223060713.28821-1-vapier@gentoo.org> MIME-Version: 1.0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Mike Frysinger via Gdb-patches From: Mike Frysinger Reply-To: Mike Frysinger Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org Sender: "Gdb-patches" There's no need for these settings to be in sim-main.h which is shared with common/ sim code, so move it all out to a new header which only this port will include. --- sim/mcore/interp.c | 2 ++ sim/mcore/mcore-sim.h | 64 +++++++++++++++++++++++++++++++++++++++++++ sim/mcore/sim-main.h | 40 --------------------------- 3 files changed, 66 insertions(+), 40 deletions(-) create mode 100644 sim/mcore/mcore-sim.h diff --git a/sim/mcore/interp.c b/sim/mcore/interp.c index 8465f56d2d7c..84b243f07059 100644 --- a/sim/mcore/interp.c +++ b/sim/mcore/interp.c @@ -38,6 +38,8 @@ along with this program. If not, see . */ #include "target-newlib-syscall.h" +#include "mcore-sim.h" + #define target_big_endian (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) diff --git a/sim/mcore/mcore-sim.h b/sim/mcore/mcore-sim.h new file mode 100644 index 000000000000..239a079ebb3a --- /dev/null +++ b/sim/mcore/mcore-sim.h @@ -0,0 +1,64 @@ +/* Simulator for Motorola's MCore processor + Copyright (C) 2009-2022 Free Software Foundation, Inc. + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . */ + +#ifndef MCORE_SIM_H +#define MCORE_SIM_H + +#include + +/* The machine state. + This state is maintained in host byte order. The + fetch/store register functions must translate between host + byte order and the target processor byte order. + Keeping this data in target byte order simplifies the register + read/write functions. Keeping this data in native order improves + the performance of the simulator. Simulation speed is deemed more + important. */ + +/* The ordering of the mcore_regset structure is matched in the + gdb/config/mcore/tm-mcore.h file in the REGISTER_NAMES macro. */ +struct mcore_regset +{ + int32_t gregs[16]; /* primary registers */ + int32_t alt_gregs[16]; /* alt register file */ + int32_t cregs[32]; /* control registers */ + int32_t pc; +}; +#define LAST_VALID_CREG 32 /* only 0..12 implemented */ +#define NUM_MCORE_REGS (16 + 16 + LAST_VALID_CREG + 1) + +struct mcore_sim_cpu { + union + { + struct mcore_regset regs; + /* Used by the fetch/store reg helpers to access registers linearly. */ + int32_t asints[NUM_MCORE_REGS]; + }; + + /* Used to switch between gregs/alt_gregs based on the control state. */ + int32_t *active_gregs; + + int ticks; + int stalls; + int cycles; + int insts; +}; + +#define MCORE_SIM_CPU(cpu) ((struct mcore_sim_cpu *) CPU_ARCH_DATA (cpu)) + +#endif diff --git a/sim/mcore/sim-main.h b/sim/mcore/sim-main.h index 684ec39354be..fc48834feb45 100644 --- a/sim/mcore/sim-main.h +++ b/sim/mcore/sim-main.h @@ -22,45 +22,5 @@ along with this program. If not, see . */ #include "sim-basics.h" #include "sim-base.h" -/* The machine state. - This state is maintained in host byte order. The - fetch/store register functions must translate between host - byte order and the target processor byte order. - Keeping this data in target byte order simplifies the register - read/write functions. Keeping this data in native order improves - the performance of the simulator. Simulation speed is deemed more - important. */ - -/* The ordering of the mcore_regset structure is matched in the - gdb/config/mcore/tm-mcore.h file in the REGISTER_NAMES macro. */ -struct mcore_regset -{ - int32_t gregs[16]; /* primary registers */ - int32_t alt_gregs[16]; /* alt register file */ - int32_t cregs[32]; /* control registers */ - int32_t pc; -}; -#define LAST_VALID_CREG 32 /* only 0..12 implemented */ -#define NUM_MCORE_REGS (16 + 16 + LAST_VALID_CREG + 1) - -struct mcore_sim_cpu { - union - { - struct mcore_regset regs; - /* Used by the fetch/store reg helpers to access registers linearly. */ - int32_t asints[NUM_MCORE_REGS]; - }; - - /* Used to switch between gregs/alt_gregs based on the control state. */ - int32_t *active_gregs; - - int ticks; - int stalls; - int cycles; - int insts; -}; - -#define MCORE_SIM_CPU(cpu) ((struct mcore_sim_cpu *) CPU_ARCH_DATA (cpu)) - #endif