diff --git a/sim/pru/pru.h b/sim/pru/pru.h
index f6b633b29bd0..375a988ddc1f 100644
--- a/sim/pru/pru.h
+++ b/sim/pru/pru.h
@@ -19,6 +19,8 @@
 #ifndef PRU_H
 #define PRU_H
 
+#include <stdint.h>
+
 #include "opcode/pru.h"
 
 /* Needed for handling the dual PRU address space.  */
@@ -108,4 +110,58 @@
 /* 32 GP registers plus PC.  */
 #define NUM_REGS	33
 
+/* The machine state.
+   This state is maintained in host byte order.  The
+   fetch/store register functions must translate between host
+   byte order and the target processor byte order.
+   Keeping this data in target byte order simplifies the register
+   read/write functions.  Keeping this data in host order improves
+   the performance of the simulator.  Simulation speed is deemed more
+   important.  */
+
+/* For clarity, please keep the same relative order in this enum as in the
+   corresponding group of GP registers.
+
+   In PRU ISA, Multiplier-Accumulator-Unit's registers are like "shadows" of
+   the GP registers.  MAC registers are implicitly addressed when executing
+   the XIN/XOUT instructions to access them.  Transfer to/from a MAC register
+   can happen only from/to its corresponding GP peer register.  */
+
+enum pru_macreg_id {
+    /* MAC register	  CPU GP register     Description.  */
+    PRU_MACREG_MODE,	  /* r25 */	      /* Mode (MUL/MAC).  */
+    PRU_MACREG_PROD_L,	  /* r26 */	      /* Lower 32 bits of product.  */
+    PRU_MACREG_PROD_H,	  /* r27 */	      /* Higher 32 bits of product.  */
+    PRU_MACREG_OP_0,	  /* r28 */	      /* First operand.  */
+    PRU_MACREG_OP_1,	  /* r29 */	      /* Second operand.  */
+    PRU_MACREG_ACC_L,	  /* N/A */	      /* Accumulator (not exposed)  */
+    PRU_MACREG_ACC_H,	  /* N/A */	      /* Higher 32 bits of MAC
+						 accumulator.  */
+    PRU_MAC_NREGS
+};
+
+struct pru_regset
+{
+  uint32_t	  regs[32];		/* Primary registers.  */
+  uint16_t	  pc;			/* IMEM _word_ address.  */
+  uint32_t	  pc_addr_space_marker; /* IMEM virtual linker offset.  This
+					   is the artificial offset that
+					   we invent in order to "separate"
+					   the DMEM and IMEM memory spaces.  */
+  unsigned int	  carry : 1;
+  uint32_t	  ctable[32];		/* Constant offsets table for xBCO.  */
+  uint32_t	  macregs[PRU_MAC_NREGS];
+  uint32_t	  scratchpads[XFRID_MAX + 1][32];
+  struct {
+    uint16_t looptop;			/* LOOP top (PC of loop instr).  */
+    uint16_t loopend;			/* LOOP end (PC of loop end label).  */
+    int loop_in_progress;		/* Whether to check for PC==loopend.  */
+    uint32_t loop_counter;		/* LOOP counter.  */
+  } loop;
+  int		  cycles;
+  int		  insts;
+};
+
+#define PRU_SIM_CPU(cpu) ((struct pru_regset *) CPU_ARCH_DATA (cpu))
+
 #endif /* PRU_H */
diff --git a/sim/pru/sim-main.h b/sim/pru/sim-main.h
index ada1e3886278..0925c3a120d9 100644
--- a/sim/pru/sim-main.h
+++ b/sim/pru/sim-main.h
@@ -19,65 +19,7 @@
 #ifndef PRU_SIM_MAIN
 #define PRU_SIM_MAIN
 
-#include <stdint.h>
-#include <stddef.h>
-#include "pru.h"
 #include "sim-basics.h"
-
 #include "sim-base.h"
 
-/* The machine state.
-   This state is maintained in host byte order.  The
-   fetch/store register functions must translate between host
-   byte order and the target processor byte order.
-   Keeping this data in target byte order simplifies the register
-   read/write functions.  Keeping this data in host order improves
-   the performance of the simulator.  Simulation speed is deemed more
-   important.  */
-
-/* For clarity, please keep the same relative order in this enum as in the
-   corresponding group of GP registers.
-
-   In PRU ISA, Multiplier-Accumulator-Unit's registers are like "shadows" of
-   the GP registers.  MAC registers are implicitly addressed when executing
-   the XIN/XOUT instructions to access them.  Transfer to/from a MAC register
-   can happen only from/to its corresponding GP peer register.  */
-
-enum pru_macreg_id {
-    /* MAC register	  CPU GP register     Description.  */
-    PRU_MACREG_MODE,	  /* r25 */	      /* Mode (MUL/MAC).  */
-    PRU_MACREG_PROD_L,	  /* r26 */	      /* Lower 32 bits of product.  */
-    PRU_MACREG_PROD_H,	  /* r27 */	      /* Higher 32 bits of product.  */
-    PRU_MACREG_OP_0,	  /* r28 */	      /* First operand.  */
-    PRU_MACREG_OP_1,	  /* r29 */	      /* Second operand.  */
-    PRU_MACREG_ACC_L,	  /* N/A */	      /* Accumulator (not exposed)  */
-    PRU_MACREG_ACC_H,	  /* N/A */	      /* Higher 32 bits of MAC
-						 accumulator.  */
-    PRU_MAC_NREGS
-};
-
-struct pru_regset
-{
-  uint32_t	  regs[32];		/* Primary registers.  */
-  uint16_t	  pc;			/* IMEM _word_ address.  */
-  uint32_t	  pc_addr_space_marker; /* IMEM virtual linker offset.  This
-					   is the artificial offset that
-					   we invent in order to "separate"
-					   the DMEM and IMEM memory spaces.  */
-  unsigned int	  carry : 1;
-  uint32_t	  ctable[32];		/* Constant offsets table for xBCO.  */
-  uint32_t	  macregs[PRU_MAC_NREGS];
-  uint32_t	  scratchpads[XFRID_MAX + 1][32];
-  struct {
-    uint16_t looptop;			/* LOOP top (PC of loop instr).  */
-    uint16_t loopend;			/* LOOP end (PC of loop end label).  */
-    int loop_in_progress;		/* Whether to check for PC==loopend.  */
-    uint32_t loop_counter;		/* LOOP counter.  */
-  } loop;
-  int		  cycles;
-  int		  insts;
-};
-
-#define PRU_SIM_CPU(cpu) ((struct pru_regset *) CPU_ARCH_DATA (cpu))
-
 #endif /* PRU_SIM_MAIN */
