From patchwork Fri Dec 23 06:07:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Frysinger X-Patchwork-Id: 62336 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D3045383EB0B for ; Fri, 23 Dec 2022 06:09:05 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D3045383EB0B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1671775745; bh=WqZLRj6P+X3idgVOyz1MEA+e2Xdw9iWrIhYRn7BysrI=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=w6Gsc2H7NcArGQVfTzJa6UEX+Y2RaKZ8xVjjtMOJN/osmdgLBtrlxZMe5eexN9SPp geh1DGgD4g1OrvCYPTWslqd2D0SXqTJyeSWds83qvfNF8LRT56fuY7sm3OOovHKxdN 8aUYmPkXi6ge2kxBSlAUa+Hjw2Ie5VnI24w7RAPY= X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from smtp.gentoo.org (dev.gentoo.org [IPv6:2001:470:ea4a:1:5054:ff:fec7:86e4]) by sourceware.org (Postfix) with ESMTP id 96D3A3850F28 for ; Fri, 23 Dec 2022 06:07:37 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 96D3A3850F28 Received: by smtp.gentoo.org (Postfix, from userid 559) id 467703411D4; Fri, 23 Dec 2022 06:07:37 +0000 (UTC) To: gdb-patches@sourceware.org Subject: [PATCH 09/20] sim: riscv: move arch-specific settings to internal header Date: Fri, 23 Dec 2022 01:07:02 -0500 Message-Id: <20221223060713.28821-10-vapier@gentoo.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221223060713.28821-1-vapier@gentoo.org> References: <20221223060713.28821-1-vapier@gentoo.org> MIME-Version: 1.0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Mike Frysinger via Gdb-patches From: Mike Frysinger Reply-To: Mike Frysinger Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org Sender: "Gdb-patches" There's no need for these settings to be in sim-main.h which is shared with common/ sim code, so move it all out to a new header which only this port will include. We can also move the machs.h include out since the model logic was all generalized from compile-time to runtime last year. --- sim/riscv/interp.c | 2 ++ sim/riscv/machs.c | 1 + sim/riscv/riscv-sim.h | 78 +++++++++++++++++++++++++++++++++++++++++++ sim/riscv/sim-main.c | 2 ++ sim/riscv/sim-main.h | 55 ------------------------------ 5 files changed, 83 insertions(+), 55 deletions(-) create mode 100644 sim/riscv/riscv-sim.h diff --git a/sim/riscv/interp.c b/sim/riscv/interp.c index 6bd0bf2a41a6..a49ad0476c45 100644 --- a/sim/riscv/interp.c +++ b/sim/riscv/interp.c @@ -27,6 +27,8 @@ #include "sim-main.h" #include "sim-options.h" #include "target-newlib-syscall.h" + +#include "riscv-sim.h" void sim_engine_run (SIM_DESC sd, diff --git a/sim/riscv/machs.c b/sim/riscv/machs.c index ea099ed02dea..4951f480e311 100644 --- a/sim/riscv/machs.c +++ b/sim/riscv/machs.c @@ -22,6 +22,7 @@ #include "defs.h" #include "sim-main.h" +#include "machs.h" static void riscv_model_init (SIM_CPU *cpu) diff --git a/sim/riscv/riscv-sim.h b/sim/riscv/riscv-sim.h new file mode 100644 index 000000000000..2139e3758c8d --- /dev/null +++ b/sim/riscv/riscv-sim.h @@ -0,0 +1,78 @@ +/* RISC-V simulator. + + Copyright (C) 2005-2022 Free Software Foundation, Inc. + Contributed by Mike Frysinger. + + This file is part of the GNU simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef RISCV_MAIN_H +#define RISCV_MAIN_H + +struct riscv_sim_cpu { + union { + unsigned_word regs[32]; + struct { + /* These are the ABI names. */ + unsigned_word zero, ra, sp, gp, tp; + unsigned_word t0, t1, t2; + unsigned_word s0, s1; + unsigned_word a0, a1, a2, a3, a4, a5, a6, a7; + unsigned_word s2, s3, s4, s5, s6, s7, s8, s9, s10, s11; + unsigned_word t3, t4, t5, t6; + }; + }; + union { + unsigned_word fpregs[32]; + struct { + /* These are the ABI names. */ + unsigned_word ft0, ft1, ft2, ft3, ft4, ft5, ft6, ft7; + unsigned_word fs0, fs1; + unsigned_word fa0, fa1, fa2, fa3, fa4, fa5, fa6, fa7; + unsigned_word fs2, fs3, fs4, fs5, fs6, fs7, fs8, fs9, fs10, fs11; + unsigned_word ft8, ft9, ft10, ft11; + }; + }; + sim_cia pc; + + struct { +#define DECLARE_CSR(name, ...) unsigned_word name; +#include "opcode/riscv-opc.h" +#undef DECLARE_CSR + } csr; +}; +#define RISCV_SIM_CPU(cpu) ((struct riscv_sim_cpu *) CPU_ARCH_DATA (cpu)) + +struct atomic_mem_reserved_list; +struct atomic_mem_reserved_list { + struct atomic_mem_reserved_list *next; + address_word addr; +}; + +struct riscv_sim_state { + struct atomic_mem_reserved_list *amo_reserved_list; +}; +#define RISCV_SIM_STATE(sd) ((struct riscv_sim_state *) STATE_ARCH_DATA (sd)) + +extern void step_once (SIM_CPU *); +extern void initialize_cpu (SIM_DESC, SIM_CPU *, int); +extern void initialize_env (SIM_DESC, const char * const *argv, + const char * const *env); + +#define DEFAULT_MEM_SIZE (64 * 1024 * 1024) + +#define RISCV_XLEN(cpu) MACH_WORD_BITSIZE (CPU_MACH (cpu)) + +#endif diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c index 4e7358b113a5..95950ee5977b 100644 --- a/sim/riscv/sim-main.c +++ b/sim/riscv/sim-main.c @@ -34,6 +34,8 @@ #include "opcode/riscv.h" #include "sim/sim-riscv.h" + +#include "riscv-sim.h" #define TRACE_REG(cpu, reg) \ TRACE_REGISTER (cpu, "wrote %s = %#" PRIxTW, riscv_gpr_names_abi[reg], \ diff --git a/sim/riscv/sim-main.h b/sim/riscv/sim-main.h index 48ea452fb0b1..a6de53cdccdb 100644 --- a/sim/riscv/sim-main.h +++ b/sim/riscv/sim-main.h @@ -22,61 +22,6 @@ #define SIM_MAIN_H #include "sim-basics.h" -#include "machs.h" #include "sim-base.h" -struct riscv_sim_cpu { - union { - unsigned_word regs[32]; - struct { - /* These are the ABI names. */ - unsigned_word zero, ra, sp, gp, tp; - unsigned_word t0, t1, t2; - unsigned_word s0, s1; - unsigned_word a0, a1, a2, a3, a4, a5, a6, a7; - unsigned_word s2, s3, s4, s5, s6, s7, s8, s9, s10, s11; - unsigned_word t3, t4, t5, t6; - }; - }; - union { - unsigned_word fpregs[32]; - struct { - /* These are the ABI names. */ - unsigned_word ft0, ft1, ft2, ft3, ft4, ft5, ft6, ft7; - unsigned_word fs0, fs1; - unsigned_word fa0, fa1, fa2, fa3, fa4, fa5, fa6, fa7; - unsigned_word fs2, fs3, fs4, fs5, fs6, fs7, fs8, fs9, fs10, fs11; - unsigned_word ft8, ft9, ft10, ft11; - }; - }; - sim_cia pc; - - struct { -#define DECLARE_CSR(name, ...) unsigned_word name; -#include "opcode/riscv-opc.h" -#undef DECLARE_CSR - } csr; -}; -#define RISCV_SIM_CPU(cpu) ((struct riscv_sim_cpu *) CPU_ARCH_DATA (cpu)) - -struct atomic_mem_reserved_list; -struct atomic_mem_reserved_list { - struct atomic_mem_reserved_list *next; - address_word addr; -}; - -struct riscv_sim_state { - struct atomic_mem_reserved_list *amo_reserved_list; -}; -#define RISCV_SIM_STATE(sd) ((struct riscv_sim_state *) STATE_ARCH_DATA (sd)) - -extern void step_once (SIM_CPU *); -extern void initialize_cpu (SIM_DESC, SIM_CPU *, int); -extern void initialize_env (SIM_DESC, const char * const *argv, - const char * const *env); - -#define DEFAULT_MEM_SIZE (64 * 1024 * 1024) - -#define RISCV_XLEN(cpu) MACH_WORD_BITSIZE (CPU_MACH (cpu)) - #endif