From patchwork Sat Nov 5 13:32:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Frysinger X-Patchwork-Id: 60019 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E28A23857C64 for ; Sat, 5 Nov 2022 13:38:33 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E28A23857C64 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1667655513; bh=EAxkAwxs3m8KdXnIsx7ktZvKAec/xW7k6/jfXnNxRGA=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=aMA5X+hVhZo6K3SFpEMLDG04Te6yryJZQ8bgnv7ATd8KrxyqRF5c8CLrGbTX8q8Y7 0MhyRqP5Rd8Of3ZTWMtCO4ZyxBLO2dWPfpSsEczjEiDxjo5BRU+V9HJQGJwH2W73Ar eRgQ9L6j+aKOwG7bRv4zVi42JriCoLE9+u9tpX1I= X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from smtp.gentoo.org (woodpecker.gentoo.org [140.211.166.183]) by sourceware.org (Postfix) with ESMTP id 57F73385800B for ; Sat, 5 Nov 2022 13:34:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 57F73385800B Received: by smtp.gentoo.org (Postfix, from userid 559) id E9C093412D2; Sat, 5 Nov 2022 13:34:01 +0000 (UTC) To: gdb-patches@sourceware.org Subject: [PATCH 26/26] sim: fully merge sim_cpu_base into sim_cpu Date: Sat, 5 Nov 2022 20:32:58 +0700 Message-Id: <20221105133258.23409-27-vapier@gentoo.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221105133258.23409-1-vapier@gentoo.org> References: <20221101151158.24916-1-vapier@gentoo.org> <20221105133258.23409-1-vapier@gentoo.org> MIME-Version: 1.0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_DMARC_STATUS, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Mike Frysinger via Gdb-patches From: Mike Frysinger Reply-To: Mike Frysinger Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org Sender: "Gdb-patches" Now that all ports have migrated to the new framework, drop support for the old sim_cpu_base layout. There's a lot of noise here, so it's been split into a dedicated commit. --- sim/common/sim-cpu.h | 45 +++++++++++++++++++------------------------- 1 file changed, 19 insertions(+), 26 deletions(-) diff --git a/sim/common/sim-cpu.h b/sim/common/sim-cpu.h index 83244e09c9ea..90e294eb3c60 100644 --- a/sim/common/sim-cpu.h +++ b/sim/common/sim-cpu.h @@ -46,39 +46,38 @@ typedef void (PC_STORE_FN) (sim_cpu *, sim_cia); /* Pseudo baseclass for each cpu. */ -typedef struct { - +struct _sim_cpu { /* Backlink to main state struct. */ SIM_DESC state; -#define CPU_STATE(cpu) ((cpu)->base.state) +#define CPU_STATE(cpu) ((cpu)->state) /* Processor index within the SD_DESC */ int index; -#define CPU_INDEX(cpu) ((cpu)->base.index) +#define CPU_INDEX(cpu) ((cpu)->index) /* The name of the cpu. */ const char *name; -#define CPU_NAME(cpu) ((cpu)->base.name) +#define CPU_NAME(cpu) ((cpu)->name) /* Options specific to this cpu. */ struct option_list *options; -#define CPU_OPTIONS(cpu) ((cpu)->base.options) +#define CPU_OPTIONS(cpu) ((cpu)->options) /* Processor specific core data */ sim_cpu_core core; -#define CPU_CORE(cpu) (& (cpu)->base.core) +#define CPU_CORE(cpu) (& (cpu)->core) /* Number of instructions (used to iterate over CPU_INSN_NAME). */ unsigned int max_insns; -#define CPU_MAX_INSNS(cpu) ((cpu)->base.max_insns) +#define CPU_MAX_INSNS(cpu) ((cpu)->max_insns) /* Function to return the name of an insn. */ CPU_INSN_NAME_FN *insn_name; -#define CPU_INSN_NAME(cpu) ((cpu)->base.insn_name) +#define CPU_INSN_NAME(cpu) ((cpu)->insn_name) /* Trace data. See sim-trace.h. */ TRACE_DATA trace_data; -#define CPU_TRACE_DATA(cpu) (& (cpu)->base.trace_data) +#define CPU_TRACE_DATA(cpu) (& (cpu)->trace_data) /* Maximum number of debuggable entities. This debugging is not intended for normal use. @@ -90,7 +89,7 @@ typedef struct { /* Boolean array of specified debugging flags. */ char debug_flags[MAX_DEBUG_VALUES]; -#define CPU_DEBUG_FLAGS(cpu) ((cpu)->base.debug_flags) +#define CPU_DEBUG_FLAGS(cpu) ((cpu)->debug_flags) /* Standard values. */ #define DEBUG_INSN_IDX 0 #define DEBUG_NEXT_IDX 2 /* simulator specific debug bits begin here */ @@ -98,37 +97,31 @@ typedef struct { /* Debugging output goes to this or stderr if NULL. We can't store `stderr' here as stderr goes through a callback. */ FILE *debug_file; -#define CPU_DEBUG_FILE(cpu) ((cpu)->base.debug_file) +#define CPU_DEBUG_FILE(cpu) ((cpu)->debug_file) /* Profile data. See sim-profile.h. */ PROFILE_DATA profile_data; -#define CPU_PROFILE_DATA(cpu) (& (cpu)->base.profile_data) +#define CPU_PROFILE_DATA(cpu) (& (cpu)->profile_data) /* Machine tables for this cpu. See sim-model.h. */ const SIM_MACH *mach; -#define CPU_MACH(cpu) ((cpu)->base.mach) +#define CPU_MACH(cpu) ((cpu)->mach) /* The selected model. */ const SIM_MODEL *model; -#define CPU_MODEL(cpu) ((cpu)->base.model) +#define CPU_MODEL(cpu) ((cpu)->model) /* Model data (profiling state, etc.). */ void *model_data; -#define CPU_MODEL_DATA(cpu) ((cpu)->base.model_data) +#define CPU_MODEL_DATA(cpu) ((cpu)->model_data) /* Routines to fetch/store registers. */ CPUREG_FETCH_FN *reg_fetch; -#define CPU_REG_FETCH(c) ((c)->base.reg_fetch) +#define CPU_REG_FETCH(c) ((c)->reg_fetch) CPUREG_STORE_FN *reg_store; -#define CPU_REG_STORE(c) ((c)->base.reg_store) +#define CPU_REG_STORE(c) ((c)->reg_store) PC_FETCH_FN *pc_fetch; -#define CPU_PC_FETCH(c) ((c)->base.pc_fetch) +#define CPU_PC_FETCH(c) ((c)->pc_fetch) PC_STORE_FN *pc_store; -#define CPU_PC_STORE(c) ((c)->base.pc_store) - -} sim_cpu_base; - -struct _sim_cpu { - /* All the common state. */ - sim_cpu_base base; +#define CPU_PC_STORE(c) ((c)->pc_store) #ifdef CGEN_ARCH /* Static parts of cgen. */