From patchwork Sat Nov 5 13:32:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Frysinger X-Patchwork-Id: 60017 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 96D613858013 for ; Sat, 5 Nov 2022 13:38:02 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 96D613858013 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1667655482; bh=RpMTf5INn3rT5U17rUIjPiWwhGCpyLYxXhdupfCQMIo=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=GCQ8MdV+468Io6Y9qQDHyWzLpLYIKcSG5BC/2wJXCRt+0x22i7Yw9T1e2g5c71I1w ejdVAtkIYu0onyMuGuX1KTA93NsdPSaWruyx4CSC68TaTNsfacRQjeIgl1HxK45BEL Hh/dAO+QcccEg1m6Ks4GeOIQy4U4QJqg161ThgF0= X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from smtp.gentoo.org (mail.gentoo.org [IPv6:2001:470:ea4a:1:5054:ff:fec7:86e4]) by sourceware.org (Postfix) with ESMTP id E63BB3857B95 for ; Sat, 5 Nov 2022 13:33:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E63BB3857B95 Received: by smtp.gentoo.org (Postfix, from userid 559) id 9A8DC3412CC; Sat, 5 Nov 2022 13:33:55 +0000 (UTC) To: gdb-patches@sourceware.org Subject: [PATCH 23/26] sim: m32r: invert sim_cpu storage Date: Sat, 5 Nov 2022 20:32:55 +0700 Message-Id: <20221105133258.23409-24-vapier@gentoo.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221105133258.23409-1-vapier@gentoo.org> References: <20221101151158.24916-1-vapier@gentoo.org> <20221105133258.23409-1-vapier@gentoo.org> MIME-Version: 1.0 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Mike Frysinger via Gdb-patches From: Mike Frysinger Reply-To: Mike Frysinger Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org Sender: "Gdb-patches" The cpu*.h changes are in generated cgen code, but that has been sent upstream too, so the next regen should include it automatically. --- sim/m32r/cpu.h | 2 +- sim/m32r/cpu2.h | 2 +- sim/m32r/cpux.h | 2 +- sim/m32r/sim-if.c | 3 ++- sim/m32r/sim-main.h | 15 +++++---------- 5 files changed, 10 insertions(+), 14 deletions(-) diff --git a/sim/m32r/cpu.h b/sim/m32r/cpu.h index 71a375f695ce..9079b74bb7d9 100644 --- a/sim/m32r/cpu.h +++ b/sim/m32r/cpu.h @@ -87,7 +87,7 @@ m32rbf_h_psw_set_handler (current_cpu, (x));\ #define GET_H_LOCK() CPU (h_lock) #define SET_H_LOCK(x) (CPU (h_lock) = (x)) } hardware; -#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware) +#define CPU_CGEN_HW(cpu) (& M32R_SIM_CPU (cpu)->cpu_data.hardware) } M32RBF_CPU_DATA; /* Cover fns for register access. */ diff --git a/sim/m32r/cpu2.h b/sim/m32r/cpu2.h index bd98a98a0c8d..5dc4d64db0cd 100644 --- a/sim/m32r/cpu2.h +++ b/sim/m32r/cpu2.h @@ -94,7 +94,7 @@ m32r2f_h_psw_set_handler (current_cpu, (x));\ #define GET_H_LOCK() CPU (h_lock) #define SET_H_LOCK(x) (CPU (h_lock) = (x)) } hardware; -#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware) +#define CPU_CGEN_HW(cpu) (& M32R_SIM_CPU (cpu)->cpu_data.hardware) } M32R2F_CPU_DATA; /* Cover fns for register access. */ diff --git a/sim/m32r/cpux.h b/sim/m32r/cpux.h index 1e6d84fc4685..f2496b075433 100644 --- a/sim/m32r/cpux.h +++ b/sim/m32r/cpux.h @@ -94,7 +94,7 @@ m32rxf_h_psw_set_handler (current_cpu, (x));\ #define GET_H_LOCK() CPU (h_lock) #define SET_H_LOCK(x) (CPU (h_lock) = (x)) } hardware; -#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware) +#define CPU_CGEN_HW(cpu) (& M32R_SIM_CPU (cpu)->cpu_data.hardware) } M32RXF_CPU_DATA; /* Cover fns for register access. */ diff --git a/sim/m32r/sim-if.c b/sim/m32r/sim-if.c index 878a0d5f5764..401d1020d704 100644 --- a/sim/m32r/sim-if.c +++ b/sim/m32r/sim-if.c @@ -66,7 +66,8 @@ sim_open (SIM_OPEN_KIND kind, host_callback *callback, struct bfd *abfd, current_target_byte_order = BFD_ENDIAN_BIG; /* The cpu data is kept in a separately allocated chunk of memory. */ - if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK) + if (sim_cpu_alloc_all_extra (sd, 1, sizeof (struct m32r_sim_cpu)) + != SIM_RC_OK) { free_state (sd); return 0; diff --git a/sim/m32r/sim-main.h b/sim/m32r/sim-main.h index 2ce989a897a1..fcde7feb61cc 100644 --- a/sim/m32r/sim-main.h +++ b/sim/m32r/sim-main.h @@ -3,6 +3,8 @@ #ifndef SIM_MAIN_H #define SIM_MAIN_H +#define SIM_HAVE_COMMON_SIM_CPU + /* This is a global setting. Different cpu families can't mix-n-match -scache and -pbb. However some cpu families may use -simple while others use one of -scache/-pbb. */ @@ -19,17 +21,9 @@ #include "m32r-sim.h" #include "opcode/cgen.h" -/* The _sim_cpu struct. */ - -struct _sim_cpu { - /* sim/common cpu base. */ - sim_cpu_base base; - - /* Static parts of cgen. */ - CGEN_CPU cgen_cpu; - +struct m32r_sim_cpu { M32R_MISC_PROFILE m32r_misc_profile; -#define CPU_M32R_MISC_PROFILE(cpu) (& (cpu)->m32r_misc_profile) +#define CPU_M32R_MISC_PROFILE(cpu) (& M32R_SIM_CPU (cpu)->m32r_misc_profile) /* CPU specific parts go here. Note that in files that don't need to access these pieces WANT_CPU_FOO @@ -47,6 +41,7 @@ struct _sim_cpu { M32R2F_CPU_DATA cpu_data; #endif }; +#define M32R_SIM_CPU(cpu) ((struct m32r_sim_cpu *) CPU_ARCH_DATA (cpu)) /* Misc. */