From patchwork Fri Nov 4 14:44:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Torbjorn SVENSSON X-Patchwork-Id: 59940 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1B31F385800A for ; Fri, 4 Nov 2022 14:45:56 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 1B31F385800A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1667573156; bh=Wg8OdBviLjb+w9GW4yK9Ez0ujnXzV7wV2h4kRYhNzIk=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=xhpH3D80LpcvCIav3k35AF4aTH4eghTrCiaAC51rkNsjkEKwQRBOzmBaoDskqLqcj K6+YACwUauy7Sz2K8DM/vl+rR+uvTHhvol3EAwcIlS0N0gZzy4OYb5ES4KUucapbIK +Jj7LbTJgTOD0WmdRuUflQ126/4FwDzSoHfeo+Vc= X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by sourceware.org (Postfix) with ESMTPS id 7C61A38582A2 for ; Fri, 4 Nov 2022 14:45:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 7C61A38582A2 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2A4B6LXe005756; Fri, 4 Nov 2022 15:45:28 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3kmpf6n5em-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 04 Nov 2022 15:45:28 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 1894310002A; Fri, 4 Nov 2022 15:45:24 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 13B9621FEA5; Fri, 4 Nov 2022 15:45:24 +0100 (CET) Received: from jkgcxl0002.jkg.st.com (10.210.54.218) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Fri, 4 Nov 2022 15:45:23 +0100 To: Subject: [PATCH 3/3] gdb/arm: PR 29738 Cache value for stack pointers for dwarf2 frames Date: Fri, 4 Nov 2022 15:44:41 +0100 Message-ID: <20221104144438.2786801-4-torbjorn.svensson@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221104144438.2786801-1-torbjorn.svensson@foss.st.com> References: <20221104144438.2786801-1-torbjorn.svensson@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.210.54.218] X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-11-04_09,2022-11-03_01,2022-06-22_01 X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: =?utf-8?q?Torbj=C3=B6rn_SVENSSON_via_Gdb-patches?= From: Torbjorn SVENSSON Reply-To: =?utf-8?q?Torbj=C3=B6rn_SVENSSON?= Cc: vanekt@volny.cz Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org Sender: "Gdb-patches" Without this patch, the number of calls to arm_dwarf2_prev_register would grow in a too rapid way when the number of frames increase. Signed-off-by: Torbjörn SVENSSON --- gdb/arm-tdep.c | 141 +++++++++++++++++++++++-------------------------- 1 file changed, 66 insertions(+), 75 deletions(-) diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index c011b2aa973..a6fb660bcbc 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -3992,78 +3992,6 @@ arm_dwarf2_prev_register (frame_info_ptr this_frame, void **this_cache, cpsr = reconstruct_t_bit (gdbarch, lr, cpsr); return frame_unwind_got_constant (this_frame, regnum, cpsr); } - else if (arm_is_alternative_sp_register (tdep, regnum)) - { - /* Handle the alternative SP registers on Cortex-M. */ - bool override_with_sp_value = false; - CORE_ADDR val; - - if (tdep->have_sec_ext) - { - CORE_ADDR sp - = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); - CORE_ADDR msp_s - = get_frame_register_unsigned (this_frame, - tdep->m_profile_msp_s_regnum); - CORE_ADDR msp_ns - = get_frame_register_unsigned (this_frame, - tdep->m_profile_msp_ns_regnum); - CORE_ADDR psp_s - = get_frame_register_unsigned (this_frame, - tdep->m_profile_psp_s_regnum); - CORE_ADDR psp_ns - = get_frame_register_unsigned (this_frame, - tdep->m_profile_psp_ns_regnum); - - bool is_msp = (regnum == tdep->m_profile_msp_regnum) - && (msp_s == sp || msp_ns == sp); - bool is_msp_s = (regnum == tdep->m_profile_msp_s_regnum) - && (msp_s == sp); - bool is_msp_ns = (regnum == tdep->m_profile_msp_ns_regnum) - && (msp_ns == sp); - bool is_psp = (regnum == tdep->m_profile_psp_regnum) - && (psp_s == sp || psp_ns == sp); - bool is_psp_s = (regnum == tdep->m_profile_psp_s_regnum) - && (psp_s == sp); - bool is_psp_ns = (regnum == tdep->m_profile_psp_ns_regnum) - && (psp_ns == sp); - - override_with_sp_value = is_msp || is_msp_s || is_msp_ns - || is_psp || is_psp_s || is_psp_ns; - - } - else if (tdep->is_m) - { - CORE_ADDR sp - = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); - CORE_ADDR msp - = get_frame_register_unsigned (this_frame, - tdep->m_profile_msp_regnum); - CORE_ADDR psp - = get_frame_register_unsigned (this_frame, - tdep->m_profile_psp_regnum); - - bool is_msp = (regnum == tdep->m_profile_msp_regnum) && (sp == msp); - bool is_psp = (regnum == tdep->m_profile_psp_regnum) && (sp == psp); - - override_with_sp_value = is_msp || is_psp; - } - - if (override_with_sp_value) - { - /* Use value of SP from previous frame. */ - frame_info_ptr prev_frame = get_prev_frame (this_frame); - if (prev_frame) - val = get_frame_register_unsigned (prev_frame, ARM_SP_REGNUM); - else - val = get_frame_base (this_frame); - } - else - /* Use value for the register from previous frame. */ - val = get_frame_register_unsigned (this_frame, regnum); - - return frame_unwind_got_constant (this_frame, regnum, val); - } internal_error (_("Unexpected register %d"), regnum); } @@ -5202,9 +5130,72 @@ arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, reg->how = DWARF2_FRAME_REG_CFA; else if (arm_is_alternative_sp_register (tdep, regnum)) { - /* Handle the alternative SP registers on Cortex-M. */ - reg->how = DWARF2_FRAME_REG_FN; - reg->loc.fn = arm_dwarf2_prev_register; + /* Identify what stack pointers that are synced with sp. */ + bool override_with_sp_value = false; + + if (tdep->have_sec_ext) + { + CORE_ADDR sp + = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); + + CORE_ADDR msp_s + = get_frame_register_unsigned (this_frame, + tdep->m_profile_msp_s_regnum); + CORE_ADDR msp_ns + = get_frame_register_unsigned (this_frame, + tdep->m_profile_msp_ns_regnum); + CORE_ADDR psp_s + = get_frame_register_unsigned (this_frame, + tdep->m_profile_psp_s_regnum); + CORE_ADDR psp_ns + = get_frame_register_unsigned (this_frame, + tdep->m_profile_psp_ns_regnum); + + bool is_msp = (regnum == tdep->m_profile_msp_regnum) + && (msp_s == sp || msp_ns == sp); + bool is_msp_s = (regnum == tdep->m_profile_msp_s_regnum) + && (msp_s == sp); + bool is_msp_ns = (regnum == tdep->m_profile_msp_ns_regnum) + && (msp_ns == sp); + bool is_psp = (regnum == tdep->m_profile_psp_regnum) + && (psp_s == sp || psp_ns == sp); + bool is_psp_s = (regnum == tdep->m_profile_psp_s_regnum) + && (psp_s == sp); + bool is_psp_ns = (regnum == tdep->m_profile_psp_ns_regnum) + && (psp_ns == sp); + + override_with_sp_value = is_msp || is_msp_s || is_msp_ns + || is_psp || is_psp_s || is_psp_ns; + + } + else if (tdep->is_m) + { + CORE_ADDR sp + = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); + + CORE_ADDR msp + = get_frame_register_unsigned (this_frame, + tdep->m_profile_msp_regnum); + CORE_ADDR psp + = get_frame_register_unsigned (this_frame, + tdep->m_profile_psp_regnum); + + bool is_msp = (regnum == tdep->m_profile_msp_regnum) && (sp == msp); + bool is_psp = (regnum == tdep->m_profile_psp_regnum) && (sp == psp); + + override_with_sp_value = is_msp || is_psp; + } + + if (override_with_sp_value) + { + /* Use the CFA value for this stack pointer register. */ + reg->how = DWARF2_FRAME_REG_CFA; + } + else + { + /* This frame does not have any update for this stack pointer. */ + reg->how = DWARF2_FRAME_REG_SAME_VALUE; + } } }