@@ -72,7 +72,7 @@ SET_H_SPR ((((index)) + (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR0))),
#define GET_H_ROFF1() CPU (h_roff1)
#define SET_H_ROFF1(x) (CPU (h_roff1) = (x))
} hardware;
-#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
+#define CPU_CGEN_HW(cpu) (& OR1K_SIM_CPU (cpu)->cpu_data.hardware)
} OR1K32BF_CPU_DATA;
/* Virtual regs. */
@@ -106,32 +106,40 @@ USI
or1k32bf_h_spr_get_raw (sim_cpu *current_cpu, USI addr)
{
SIM_DESC sd = CPU_STATE (current_cpu);
+ struct or1k_sim_cpu *or1k_cpu = OR1K_SIM_CPU (current_cpu);
+
SIM_ASSERT (addr < NUM_SPR);
- return current_cpu->spr[addr];
+ return or1k_cpu->spr[addr];
}
void
or1k32bf_h_spr_set_raw (sim_cpu *current_cpu, USI addr, USI val)
{
SIM_DESC sd = CPU_STATE (current_cpu);
+ struct or1k_sim_cpu *or1k_cpu = OR1K_SIM_CPU (current_cpu);
+
SIM_ASSERT (addr < NUM_SPR);
- current_cpu->spr[addr] = val;
+ or1k_cpu->spr[addr] = val;
}
USI
or1k32bf_h_spr_field_get_raw (sim_cpu *current_cpu, USI addr, int msb, int lsb)
{
SIM_DESC sd = CPU_STATE (current_cpu);
+ struct or1k_sim_cpu *or1k_cpu = OR1K_SIM_CPU (current_cpu);
+
SIM_ASSERT (addr < NUM_SPR);
- return LSEXTRACTED (current_cpu->spr[addr], msb, lsb);
+ return LSEXTRACTED (or1k_cpu->spr[addr], msb, lsb);
}
void
or1k32bf_h_spr_field_set_raw (sim_cpu *current_cpu, USI addr, int msb, int lsb,
USI val)
{
- current_cpu->spr[addr] &= ~LSMASK32 (msb, lsb);
- current_cpu->spr[addr] |= LSINSERTED (val, msb, lsb);
+ struct or1k_sim_cpu *or1k_cpu = OR1K_SIM_CPU (current_cpu);
+
+ or1k_cpu->spr[addr] &= ~LSMASK32 (msb, lsb);
+ or1k_cpu->spr[addr] |= LSINSERTED (val, msb, lsb);
}
/* Initialize a sim cpu object. */
@@ -139,6 +147,8 @@ void
or1k_cpu_init (SIM_DESC sd, sim_cpu *current_cpu, const USI or1k_vr,
const USI or1k_upr, const USI or1k_cpucfgr)
{
+ struct or1k_sim_cpu *or1k_cpu = OR1K_SIM_CPU (current_cpu);
+
/* Set the configuration registers passed from the user. */
SET_H_SYS_VR (or1k_vr);
SET_H_SYS_UPR (or1k_upr);
@@ -155,8 +165,8 @@ or1k_cpu_init (SIM_DESC sd, sim_cpu *current_cpu, const USI or1k_vr,
} while (0)
/* Set flags indicating if we are in a delay slot or not. */
- current_cpu->next_delay_slot = 0;
- current_cpu->delay_slot = 0;
+ or1k_cpu->next_delay_slot = 0;
+ or1k_cpu->delay_slot = 0;
/* Verify any user passed fields and warn on configurations we don't
support. */
@@ -204,11 +214,12 @@ void
or1k32bf_insn_before (sim_cpu *current_cpu, SEM_PC vpc, const IDESC *idesc)
{
SIM_DESC sd = CPU_STATE (current_cpu);
+ struct or1k_sim_cpu *or1k_cpu = OR1K_SIM_CPU (current_cpu);
- current_cpu->delay_slot = current_cpu->next_delay_slot;
- current_cpu->next_delay_slot = 0;
+ or1k_cpu->delay_slot = or1k_cpu->next_delay_slot;
+ or1k_cpu->next_delay_slot = 0;
- if (current_cpu->delay_slot &&
+ if (or1k_cpu->delay_slot &&
CGEN_ATTR_BOOLS (CGEN_INSN_ATTRS ((idesc)->idata)) &
CGEN_ATTR_MASK (CGEN_INSN_NOT_IN_DELAY_SLOT))
{
@@ -228,6 +239,7 @@ void
or1k32bf_insn_after (sim_cpu *current_cpu, SEM_PC vpc, const IDESC *idesc)
{
SIM_DESC sd = CPU_STATE (current_cpu);
+ struct or1k_sim_cpu *or1k_cpu = OR1K_SIM_CPU (current_cpu);
USI ppc;
#ifdef WITH_SCACHE
@@ -242,8 +254,8 @@ or1k32bf_insn_after (sim_cpu *current_cpu, SEM_PC vpc, const IDESC *idesc)
CGEN_ATTR_BOOLS (CGEN_INSN_ATTRS ((idesc)->idata)) &
CGEN_ATTR_MASK (CGEN_INSN_DELAYED_CTI))
{
- SIM_ASSERT (!current_cpu->delay_slot);
- current_cpu->next_delay_slot = 1;
+ SIM_ASSERT (!or1k_cpu->delay_slot);
+ or1k_cpu->next_delay_slot = 1;
}
}
@@ -19,6 +19,8 @@
#ifndef SIM_MAIN_H
#define SIM_MAIN_H
+#define SIM_HAVE_COMMON_SIM_CPU
+
#define WITH_SCACHE_PBB 1
#include "ansidecl.h"
@@ -35,17 +37,10 @@
#define OR1K_DEFAULT_MEM_SIZE 0x800000 /* 8M */
-/* The _sim_cpu struct. */
-struct _sim_cpu
+struct or1k_sim_cpu
{
- /* sim/common cpu base. */
- sim_cpu_base base;
-
- /* Static parts of cgen. */
- CGEN_CPU cgen_cpu;
-
OR1K_MISC_PROFILE or1k_misc_profile;
-#define CPU_OR1K_MISC_PROFILE(cpu) (& (cpu)->or1k_misc_profile)
+#define CPU_OR1K_MISC_PROFILE(cpu) (& OR1K_SIM_CPU (cpu)->or1k_misc_profile)
/* CPU specific parts go here.
Note that in files that don't need to access these pieces WANT_CPU_FOO
@@ -65,5 +60,6 @@ struct _sim_cpu
OR1K32BF_CPU_DATA cpu_data;
#endif
};
+#define OR1K_SIM_CPU(cpu) ((struct or1k_sim_cpu *) CPU_ARCH_DATA (cpu))
#endif /* SIM_MAIN_H */
@@ -123,6 +123,7 @@ void
or1k32bf_exception (sim_cpu *current_cpu, USI pc, USI exnum)
{
SIM_DESC sd = CPU_STATE (current_cpu);
+ struct or1k_sim_cpu *or1k_cpu = OR1K_SIM_CPU (current_cpu);
if (exnum == EXCEPT_TRAP)
{
@@ -142,14 +143,14 @@ or1k32bf_exception (sim_cpu *current_cpu, USI pc, USI exnum)
case EXCEPT_FPE:
case EXCEPT_SYSCALL:
- SET_H_SYS_EPCR0 (pc + 4 - (current_cpu->delay_slot ? 4 : 0));
+ SET_H_SYS_EPCR0 (pc + 4 - (or1k_cpu->delay_slot ? 4 : 0));
break;
case EXCEPT_BUSERR:
case EXCEPT_ALIGN:
case EXCEPT_ILLEGAL:
case EXCEPT_RANGE:
- SET_H_SYS_EPCR0 (pc - (current_cpu->delay_slot ? 4 : 0));
+ SET_H_SYS_EPCR0 (pc - (or1k_cpu->delay_slot ? 4 : 0));
break;
default:
@@ -162,9 +163,9 @@ or1k32bf_exception (sim_cpu *current_cpu, USI pc, USI exnum)
SET_H_SYS_ESR0 (GET_H_SYS_SR ());
/* Indicate in SR if the failed instruction is in delay slot or not. */
- SET_H_SYS_SR_DSX (current_cpu->delay_slot);
+ SET_H_SYS_SR_DSX (or1k_cpu->delay_slot);
- current_cpu->next_delay_slot = 0;
+ or1k_cpu->next_delay_slot = 0;
/* Jump program counter into handler. */
handler_pc =
@@ -180,10 +181,12 @@ or1k32bf_exception (sim_cpu *current_cpu, USI pc, USI exnum)
void
or1k32bf_rfe (sim_cpu *current_cpu)
{
+ struct or1k_sim_cpu *or1k_cpu = OR1K_SIM_CPU (current_cpu);
+
SET_H_SYS_SR (GET_H_SYS_ESR0 ());
SET_H_SYS_SR_FO (1);
- current_cpu->next_delay_slot = 0;
+ or1k_cpu->next_delay_slot = 0;
sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
GET_H_SYS_EPCR0 ());
@@ -246,6 +249,7 @@ void
or1k32bf_mtspr (sim_cpu *current_cpu, USI addr, USI val)
{
SIM_DESC sd = CPU_STATE (current_cpu);
+ struct or1k_sim_cpu *or1k_cpu = OR1K_SIM_CPU (current_cpu);
if (!GET_H_SYS_SR_SM () && !GET_H_SYS_SR_SUMRA ())
{
@@ -275,9 +279,9 @@ or1k32bf_mtspr (sim_cpu *current_cpu, USI addr, USI val)
break;
case SPR_ADDR (SYS, NPC):
- current_cpu->next_delay_slot = 0;
+ or1k_cpu->next_delay_slot = 0;
- sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL, val);
+ sim_engine_restart (sd, current_cpu, NULL, val);
break;
case SPR_ADDR (TICK, TTMR):