From patchwork Tue Nov 1 15:11:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Frysinger X-Patchwork-Id: 59736 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E686F38555B8 for ; Tue, 1 Nov 2022 16:28:53 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E686F38555B8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1667320133; bh=/HN39jaijYTrkLmawhZfFi/qxmn+adjIlEeNoeI5caQ=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=ESPcTHDjInX8NiW0DLBi8TB5Zlns7NropUdt6tG8oji1oa7T1qjJT0l1gDT6pJDSr /NxSrKMDoHb+UBqweInPsUt9NCYhgdctVSH8IJVmEmlEVKBU0h6JhKGsvAclnoQc8f KsBAk0Dat5xzQOJ/nQkLRbQGnlVrZrFZUn79bYBg= X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from smtp.gentoo.org (woodpecker.gentoo.org [140.211.166.183]) by sourceware.org (Postfix) with ESMTP id 2551A385624D for ; Tue, 1 Nov 2022 16:27:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 2551A385624D Received: by smtp.gentoo.org (Postfix, from userid 559) id C73A3340DA4; Tue, 1 Nov 2022 16:27:07 +0000 (UTC) To: gdb-patches@sourceware.org Subject: [PATCH 21/27] sim: frv: invert sim_cpu storage Date: Tue, 1 Nov 2022 20:56:52 +0545 Message-Id: <20221101151158.24916-22-vapier@gentoo.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221101151158.24916-1-vapier@gentoo.org> References: <20221101151158.24916-1-vapier@gentoo.org> MIME-Version: 1.0 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Mike Frysinger via Gdb-patches From: Mike Frysinger Reply-To: Mike Frysinger Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org Sender: "Gdb-patches" The cpu.h change is in generated cgen code, but that has been sent upstream too, so the next regen should include it automatically. --- sim/frv/cpu.h | 2 +- sim/frv/sim-main.h | 37 ++++++++++++++++--------------------- 2 files changed, 17 insertions(+), 22 deletions(-) diff --git a/sim/frv/cpu.h b/sim/frv/cpu.h index 902c6d4ae48d..d2409131b659 100644 --- a/sim/frv/cpu.h +++ b/sim/frv/cpu.h @@ -158,7 +158,7 @@ frvbf_h_spr_set_handler (current_cpu, (index), (x));\ #define GET_H_CCCR(a1) CPU (h_cccr)[a1] #define SET_H_CCCR(a1, x) (CPU (h_cccr)[a1] = (x)) } hardware; -#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware) +#define CPU_CGEN_HW(cpu) (& FRV_SIM_CPU (cpu)->cpu_data.hardware) } FRVBF_CPU_DATA; /* Virtual regs. */ diff --git a/sim/frv/sim-main.h b/sim/frv/sim-main.h index 01ef0b680b90..3e40bd52ab38 100644 --- a/sim/frv/sim-main.h +++ b/sim/frv/sim-main.h @@ -22,6 +22,8 @@ along with this program. If not, see . */ /* Main header for the frv. */ +#define SIM_HAVE_COMMON_SIM_CPU + /* This is a global setting. Different cpu families can't mix-n-match -scache and -pbb. However some cpu families may use -simple while others use one of -scache/-pbb. ???? */ @@ -51,15 +53,7 @@ void frv_sim_engine_halt_hook (SIM_DESC, SIM_CPU *, sim_cia); extern void frv_sim_close (SIM_DESC sd, int quitting); #define SIM_CLOSE_HOOK(...) frv_sim_close (__VA_ARGS__) -/* The _sim_cpu struct. */ - -struct _sim_cpu { - /* sim/common cpu base. */ - sim_cpu_base base; - - /* Static parts of cgen. */ - CGEN_CPU cgen_cpu; - +struct frv_sim_cpu { /* CPU specific parts go here. Note that in files that don't need to access these pieces WANT_CPU_FOO won't be defined and thus these parts won't appear. This is ok in the @@ -72,40 +66,41 @@ struct _sim_cpu { /* Control information for registers */ FRV_REGISTER_CONTROL register_control; -#define CPU_REGISTER_CONTROL(cpu) (& (cpu)->register_control) +#define CPU_REGISTER_CONTROL(cpu) (& FRV_SIM_CPU (cpu)->register_control) FRV_VLIW vliw; -#define CPU_VLIW(cpu) (& (cpu)->vliw) +#define CPU_VLIW(cpu) (& FRV_SIM_CPU (cpu)->vliw) FRV_CACHE insn_cache; -#define CPU_INSN_CACHE(cpu) (& (cpu)->insn_cache) +#define CPU_INSN_CACHE(cpu) (& FRV_SIM_CPU (cpu)->insn_cache) FRV_CACHE data_cache; -#define CPU_DATA_CACHE(cpu) (& (cpu)->data_cache) +#define CPU_DATA_CACHE(cpu) (& FRV_SIM_CPU (cpu)->data_cache) FRV_PROFILE_STATE profile_state; -#define CPU_PROFILE_STATE(cpu) (& (cpu)->profile_state) +#define CPU_PROFILE_STATE(cpu) (& FRV_SIM_CPU (cpu)->profile_state) int debug_state; -#define CPU_DEBUG_STATE(cpu) ((cpu)->debug_state) +#define CPU_DEBUG_STATE(cpu) (FRV_SIM_CPU (cpu)->debug_state) SI load_address; -#define CPU_LOAD_ADDRESS(cpu) ((cpu)->load_address) +#define CPU_LOAD_ADDRESS(cpu) (FRV_SIM_CPU (cpu)->load_address) SI load_length; -#define CPU_LOAD_LENGTH(cpu) ((cpu)->load_length) +#define CPU_LOAD_LENGTH(cpu) (FRV_SIM_CPU (cpu)->load_length) SI load_flag; -#define CPU_LOAD_SIGNED(cpu) ((cpu)->load_flag) -#define CPU_LOAD_LOCK(cpu) ((cpu)->load_flag) +#define CPU_LOAD_SIGNED(cpu) (FRV_SIM_CPU (cpu)->load_flag) +#define CPU_LOAD_LOCK(cpu) (FRV_SIM_CPU (cpu)->load_flag) SI store_flag; -#define CPU_RSTR_INVALIDATE(cpu) ((cpu)->store_flag) +#define CPU_RSTR_INVALIDATE(cpu) (FRV_SIM_CPU (cpu)->store_flag) unsigned long elf_flags; -#define CPU_ELF_FLAGS(cpu) ((cpu)->elf_flags) +#define CPU_ELF_FLAGS(cpu) (FRV_SIM_CPU (cpu)->elf_flags) #endif /* defined (WANT_CPU_FRVBF) */ }; +#define FRV_SIM_CPU(cpu) ((struct frv_sim_cpu *) CPU_ARCH_DATA (cpu)) /* Misc. */