From patchwork Tue Dec 4 13:29:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Burgess X-Patchwork-Id: 30532 Received: (qmail 13698 invoked by alias); 4 Dec 2018 13:29:45 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 13668 invoked by uid 89); 4 Dec 2018 13:29:44 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=Hx-languages-length:1349 X-HELO: mail-wr1-f68.google.com Received: from mail-wr1-f68.google.com (HELO mail-wr1-f68.google.com) (209.85.221.68) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 04 Dec 2018 13:29:42 +0000 Received: by mail-wr1-f68.google.com with SMTP id j2so15977063wrw.1 for ; Tue, 04 Dec 2018 05:29:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; h=from:to:cc:subject:date:message-id; bh=WkD/C1+pZs7a4Er4ABFcc/EWKBRNEygrLu7EMA5jmPg=; b=VEzmKEv4PVViwHpYGQ6fWRaryIxJNDUdxumAgcpi39kb6rHFN/6vPSVUpS671yM759 pfC3ztpes1IJ/OrMhQbr9MZEUgdcDmBqWXgxSW6lj2iAngJrfOlqHYljz87iDulC/7Ea QixlCDU+T/ukiX8BUgWyUTya+bYv4HAP6ue39PGrxGjQfQYu4vwz+f41CizKcD9HvZlD OX2hcs3J16fDd5Hg7zoImftNmELY6PFZmEIDHwKAKLCaXhybKSzLWXBDhGhbgSWRhU2l 1BEyVNAIhDfv3UJlNtlQdW+zw2lofHcByKEdfiND9+QktNVgjWjUh9XMqYpDzGMaAIIV SO2Q== Return-Path: Received: from localhost (host86-156-236-210.range86-156.btcentralplus.com. [86.156.236.210]) by smtp.gmail.com with ESMTPSA id t131sm12708306wmt.1.2018.12.04.05.29.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 04 Dec 2018 05:29:38 -0800 (PST) From: Andrew Burgess To: gdb-patches@sourceware.org Cc: jimw@sifive.com, palmer@sifive.com, jhb@FreeBSD.org, Andrew Burgess Subject: [PATCH] gdb/riscv: Update test to handle targets without an fpu Date: Tue, 4 Dec 2018 13:29:34 +0000 Message-Id: <20181204132934.26104-1-andrew.burgess@embecosm.com> X-IsSubscribed: yes The FPU is optional on RISC-V. The gdb.base/float.exp test currently assumes that an fpu is always available on RISC-V. Update the test so that this is not the case. gdb/testsuite/ChangeLog: * gdb.base/float.exp: Handle RISC-V targets without an FPU. --- gdb/testsuite/ChangeLog | 4 ++++ gdb/testsuite/gdb.base/float.exp | 10 +++++++++- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/gdb/testsuite/gdb.base/float.exp b/gdb/testsuite/gdb.base/float.exp index 71d3f60c499..23d68a13dfc 100644 --- a/gdb/testsuite/gdb.base/float.exp +++ b/gdb/testsuite/gdb.base/float.exp @@ -111,7 +111,15 @@ if { [is_aarch64_target] } then { } elseif [istarget "sparc*-*-*"] then { gdb_test "info float" "f0.*f1.*f31.*d0.*d30.*" "info float" } elseif [istarget "riscv*-*-*"] then { - gdb_test "info float" "ft0.*ft1.*ft11.*fflags.*frm.*fcsr.*" "info float" + # RISC-V may or may not have an FPU + gdb_test_multiple "info float" "info float" { + -re "ft0.*ft1.*ft11.*fflags.*frm.*fcsr.*$gdb_prompt $" { + pass "info float (with FPU)" + } + -re "No floating.point info available for this processor.*$gdb_prompt $" { + pass "info float (without FPU)" + } + } } else { gdb_test "info float" "No floating.point info available for this processor." "info float (unknown target)" }