From patchwork Thu Oct 25 23:59:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Wilson X-Patchwork-Id: 29899 Received: (qmail 42137 invoked by alias); 25 Oct 2018 23:59:41 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 42126 invoked by uid 89); 25 Oct 2018 23:59:40 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.0 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=H*f:sk:CAFyWVa, UD:riscv-tdep.h, Refer, riscvtdeph X-HELO: mail-pl1-f193.google.com Received: from mail-pl1-f193.google.com (HELO mail-pl1-f193.google.com) (209.85.214.193) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 25 Oct 2018 23:59:39 +0000 Received: by mail-pl1-f193.google.com with SMTP id 30-v6so4599536plb.10 for ; Thu, 25 Oct 2018 16:59:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BdrM0baN5kkRQeasoakRQYL13yOOtXeDykkBTzHuUC4=; b=GDe0u4kKl3E4kdEf7ttp0CKKXbO1JF+ILm6/DyIAYfoHRpvab1tDaf/b2u9Sq7tWKY r76y061wruM3rMz2AlxVeuJZufqsxA2xxbpM+v3clwD5oufaSMjioToEFvWZz+5IoTm1 RX3mYPtd0kUwS7alCUFsmIaaStJ0O8NZpFx/RPwsgTGf0Au+EYTg9L8Xhbbl1uorPONq qsgqf+PD1V7XhQrOybJ5x/4sRs+jV6CFhZnelR0Ex0zA+NeTkiug0VZnyvbSLZmtQrrP ukYcVpD9dqFGA3ruPXi//E0P0UPOC3CKz890+tEjI971sc/Ew2knyDlXS2B3L2/bb1sG JGTw== Return-Path: Received: from rohan.internal.sifive.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id 68-v6sm11216643pfg.136.2018.10.25.16.59.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Oct 2018 16:59:37 -0700 (PDT) From: Jim Wilson To: gdb-patches@sourceware.org Cc: Jim Wilson Subject: [PATCH 1/2] RISC-V: Linux signal frame support. Date: Thu, 25 Oct 2018 16:59:35 -0700 Message-Id: <20181025235935.3781-1-jimw@sifive.com> In-Reply-To: References: Make riscv_isa_flen available to the linux native code, and clean up duplicate comments. gdb/ * riscv-tdep.c (riscv_isa_xlen): Refer to riscv-tdep.h comment. (riscv_isa_flen): Likewise. Drop static. * riscv-tdep.h (riscv_isa_xlen): Move riscv-tdep.c comment to here. (riscv_isa_flen): Likewise. --- gdb/riscv-tdep.c | 11 +++-------- gdb/riscv-tdep.h | 11 ++++++++++- 2 files changed, 13 insertions(+), 9 deletions(-) diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c index f02420dfe5..a58c59765e 100644 --- a/gdb/riscv-tdep.c +++ b/gdb/riscv-tdep.c @@ -342,9 +342,7 @@ riscv_has_feature (struct gdbarch *gdbarch, char feature) return (misa & (1 << (feature - 'A'))) != 0; } -/* Return the width in bytes of the general purpose registers for GDBARCH. - Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or - RV128. */ +/* See riscv-tdep.h. */ int riscv_isa_xlen (struct gdbarch *gdbarch) @@ -363,12 +361,9 @@ riscv_isa_xlen (struct gdbarch *gdbarch) } } -/* Return the width in bytes of the floating point registers for GDBARCH. - If this architecture has no floating point registers, then return 0. - Possible values are 4, 8, or 16 for depending on which of single, double - or quad floating point support is available. */ +/* See riscv-tdep.h. */ -static int +int riscv_isa_flen (struct gdbarch *gdbarch) { if (riscv_has_feature (gdbarch, 'Q')) diff --git a/gdb/riscv-tdep.h b/gdb/riscv-tdep.h index e04e728f32..2cb51b16c5 100644 --- a/gdb/riscv-tdep.h +++ b/gdb/riscv-tdep.h @@ -84,9 +84,18 @@ struct gdbarch_tdep struct type *riscv_fpreg_q_type; }; -/* Return the width in bytes of the general purpose registers for GDBARCH. */ + +/* Return the width in bytes of the general purpose registers for GDBARCH. + Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or + RV128. */ extern int riscv_isa_xlen (struct gdbarch *gdbarch); +/* Return the width in bytes of the floating point registers for GDBARCH. + If this architecture has no floating point registers, then return 0. + Possible values are 4, 8, or 16 for depending on which of single, double + or quad floating point support is available. */ +extern int riscv_isa_flen (struct gdbarch *gdbarch); + /* Single step based on where the current instruction will take us. */ extern std::vector riscv_software_single_step (struct regcache *regcache);