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[1/2] RISC-V: Linux signal frame support.

Message ID 20181025235935.3781-1-jimw@sifive.com
State New, archived
Headers

Commit Message

Jim Wilson Oct. 25, 2018, 11:59 p.m. UTC 
  Make riscv_isa_flen available to the linux native code, and clean up duplicate
comments.

	gdb/
	* riscv-tdep.c (riscv_isa_xlen): Refer to riscv-tdep.h comment.
	(riscv_isa_flen): Likewise.  Drop static.
	* riscv-tdep.h (riscv_isa_xlen): Move riscv-tdep.c comment to here.
	(riscv_isa_flen): Likewise.
---
 gdb/riscv-tdep.c | 11 +++--------
 gdb/riscv-tdep.h | 11 ++++++++++-
 2 files changed, 13 insertions(+), 9 deletions(-)

Comments

Kevin Buettner Oct. 26, 2018, 3:25 a.m. UTC | #1 
On Thu, 25 Oct 2018 16:59:35 -0700
Jim Wilson <jimw@sifive.com> wrote:

> Make riscv_isa_flen available to the linux native code, and clean up duplicate
> comments.
> 
> 	gdb/
> 	* riscv-tdep.c (riscv_isa_xlen): Refer to riscv-tdep.h comment.
> 	(riscv_isa_flen): Likewise.  Drop static.
> 	* riscv-tdep.h (riscv_isa_xlen): Move riscv-tdep.c comment to here.
> 	(riscv_isa_flen): Likewise.

Maybe:

	(riscv_isa_flen): Likewise; declare.

?

Otherwise, LGTM.

Kevin
Jim Wilson Oct. 26, 2018, 5:34 p.m. UTC | #2 
On Thu, Oct 25, 2018 at 8:25 PM Kevin Buettner <kevinb@redhat.com> wrote:
>
> On Thu, 25 Oct 2018 16:59:35 -0700
> Jim Wilson <jimw@sifive.com> wrote:
>
> > Make riscv_isa_flen available to the linux native code, and clean up duplicate
> > comments.
> >
> >       gdb/
> >       * riscv-tdep.c (riscv_isa_xlen): Refer to riscv-tdep.h comment.
> >       (riscv_isa_flen): Likewise.  Drop static.
> >       * riscv-tdep.h (riscv_isa_xlen): Move riscv-tdep.c comment to here.
> >       (riscv_isa_flen): Likewise.
>
> Maybe:
>
>         (riscv_isa_flen): Likewise; declare.
>
> ?
>
> Otherwise, LGTM.

Thanks.  Committed with the corrected ChangeLog entry.

Jim
diff mbox

Patch

diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index f02420dfe5..a58c59765e 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -342,9 +342,7 @@  riscv_has_feature (struct gdbarch *gdbarch, char feature)
   return (misa & (1 << (feature - 'A'))) != 0;
 }
 
-/* Return the width in bytes  of the general purpose registers for GDBARCH.
-   Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or
-   RV128.  */
+/* See riscv-tdep.h.  */
 
 int
 riscv_isa_xlen (struct gdbarch *gdbarch)
@@ -363,12 +361,9 @@  riscv_isa_xlen (struct gdbarch *gdbarch)
     }
 }
 
-/* Return the width in bytes of the floating point registers for GDBARCH.
-   If this architecture has no floating point registers, then return 0.
-   Possible values are 4, 8, or 16 for depending on which of single, double
-   or quad floating point support is available.  */
+/* See riscv-tdep.h.  */
 
-static int
+int
 riscv_isa_flen (struct gdbarch *gdbarch)
 {
   if (riscv_has_feature (gdbarch, 'Q'))
diff --git a/gdb/riscv-tdep.h b/gdb/riscv-tdep.h
index e04e728f32..2cb51b16c5 100644
--- a/gdb/riscv-tdep.h
+++ b/gdb/riscv-tdep.h
@@ -84,9 +84,18 @@  struct gdbarch_tdep
   struct type *riscv_fpreg_q_type;
 };
 
-/* Return the width in bytes of the general purpose registers for GDBARCH.  */
+
+/* Return the width in bytes  of the general purpose registers for GDBARCH.
+   Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or
+   RV128.  */
 extern int riscv_isa_xlen (struct gdbarch *gdbarch);
 
+/* Return the width in bytes of the floating point registers for GDBARCH.
+   If this architecture has no floating point registers, then return 0.
+   Possible values are 4, 8, or 16 for depending on which of single, double
+   or quad floating point support is available.  */
+extern int riscv_isa_flen (struct gdbarch *gdbarch);
+
 /* Single step based on where the current instruction will take us.  */
 extern std::vector<CORE_ADDR> riscv_software_single_step
   (struct regcache *regcache);