From patchwork Thu Oct 25 11:09:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Burgess X-Patchwork-Id: 29885 Received: (qmail 47937 invoked by alias); 25 Oct 2018 11:09:53 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 47926 invoked by uid 89); 25 Oct 2018 11:09:52 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.4 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=HX-Google-Smtp-Source:AJdET5d X-HELO: mail-wr1-f68.google.com Received: from mail-wr1-f68.google.com (HELO mail-wr1-f68.google.com) (209.85.221.68) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 25 Oct 2018 11:09:51 +0000 Received: by mail-wr1-f68.google.com with SMTP id g9-v6so8856381wrq.4 for ; Thu, 25 Oct 2018 04:09:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=V56hJnKKThH1PqXUNPt00vJCWpTzp0+rZpJ3kXu37dU=; b=QMBwB+LWqwf+V5o1lVWDOpWaUCzWLtdRLDhoyj/hXV9rFp4V/LOhbK3fG63+erwxeV zuR4N1hrBShGAYtaUn45Y8ibsP89rt0GMPmZ9wICY4/7or7PkKXjic86P8OVZqR24xoC cI/vTJ0mAUtR7iGibWdbRdGaF8Gol4HwgYLoV6J0QyfewTKzY6vGd6fETqAgi/zpa8L6 YZdtSYiWi0RFvXDuv70swEorvjbJUDcysPsIFh0xWFPXx/pE1N0cg2Hw2MLnCOzAnhOv D4f6XX7TqLexp1UjbKfsGUUSuFiuGJK1ceTzW4MAsqRIt7TL6XrMArpKHi6ZmmK5n2v2 03hg== Return-Path: Received: from localhost (host86-164-85-193.range86-164.btcentralplus.com. [86.164.85.193]) by smtp.gmail.com with ESMTPSA id o201-v6sm1391824wmg.16.2018.10.25.04.09.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 25 Oct 2018 04:09:48 -0700 (PDT) Date: Thu, 25 Oct 2018 12:09:47 +0100 From: Andrew Burgess To: Andreas Schwab Cc: Jim Wilson , gdb-patches@sourceware.org Subject: Re: [PATCH 4/5] RISC-V: Add native linux support. Message-ID: <20181025110946.GN2929@embecosm.com> References: <20180808233908.8149-1-jimw@sifive.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Fortune: Help a swallow land at Capistrano. X-Editor: GNU Emacs [ http://www.gnu.org/software/emacs ] User-Agent: Mutt/1.9.2 (2017-12-15) X-IsSubscribed: yes * Andreas Schwab [2018-10-25 12:49:09 +0200]: > On Aug 08 2018, Jim Wilson wrote: > > > + if ((regnum == RISCV_CSR_MISA_REGNUM) > > + || (regnum == -1)) > > + { > > + /* TODO: Need to add a ptrace call for this. */ > > + regcache->raw_supply_zeroed (regnum); > > ../../gdb/gdb/regcache.c:337: internal-error: void reg_buffer::assert_regnum(int) const: Assertion `regnum >= 0' failed. Thanks for the report. I pushed the patch below to fix this issue. Thanks, Andrew --- [PATCH] gdb/riscv: Use correct regnum in riscv_linux_nat_target::fetch_registers In riscv_linux_nat_target::fetch_registers, if we are asked to supply all registers (regnum parameter is -1), then we currently end up calling regcache::raw_supply_zeroed with the regnum -1, which is invalid. Instead we should be passing the regnum of the specific register we wish to supply zeroed, in this case RISCV_CSR_MISA_REGNUM. I removed the extra { ... } block in line with the coding standard while editing this area. gdb/ChangeLog: * riscv-linux-nat.c (riscv_linux_nat_target::fetch_registers): Pass correct regnum to raw_supply_zeroed. --- gdb/ChangeLog | 5 +++++ gdb/riscv-linux-nat.c | 6 ++---- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/gdb/riscv-linux-nat.c b/gdb/riscv-linux-nat.c index 7dbfe651f2c..c09121d052b 100644 --- a/gdb/riscv-linux-nat.c +++ b/gdb/riscv-linux-nat.c @@ -201,10 +201,8 @@ riscv_linux_nat_target::fetch_registers (struct regcache *regcache, int regnum) if ((regnum == RISCV_CSR_MISA_REGNUM) || (regnum == -1)) - { - /* TODO: Need to add a ptrace call for this. */ - regcache->raw_supply_zeroed (regnum); - } + /* TODO: Need to add a ptrace call for this. */ + regcache->raw_supply_zeroed (RISCV_CSR_MISA_REGNUM); /* Access to other CSRs has potential security issues, don't support them for now. */