From patchwork Wed Aug 8 18:34:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Wilson X-Patchwork-Id: 28798 Received: (qmail 24823 invoked by alias); 8 Aug 2018 18:35:08 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 24801 invoked by uid 89); 8 Aug 2018 18:35:07 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.0 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-pg1-f193.google.com Received: from mail-pg1-f193.google.com (HELO mail-pg1-f193.google.com) (209.85.215.193) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 08 Aug 2018 18:35:06 +0000 Received: by mail-pg1-f193.google.com with SMTP id n7-v6so1486182pgq.4 for ; Wed, 08 Aug 2018 11:35:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=sAwMCoLl3ENNGtEyJE4frmWVCRxk+bF4t2lahaAo8Gs=; b=Gjqnn5kpoDVFBgFotzmhnFhiTbVSKndk/joOjxQDIGreSFy6iDRpHf5p5KWqkvUKpV efnAh+I6ihgYuuLunMKBmxIcCUmR4zxWD2lZnSH2eYjq90b9iuFMojdAVKAVVXjN079O vcZpzSDC5gLpBN6QkN4zSkN6KfQCO/e9HHo3srnwF2LVRIi8YFm/PQ3HKi9/5j0Vhzn9 ha4MS1hg6LvYeoPm5Tk3BxpI3wwhHywzqRdzf4PgM0HRQZnhy/Co33Ki954DjVgPcjgc ukPwWRqdH2cIvtOgZwAKqaq8B6ZPAWx3kCGXxvj74qyYulBkgPg8jgGO7hOJhD2uJ23Z yedA== Return-Path: Received: from rohan.internal.sifive.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id v30-v6sm8566178pgn.80.2018.08.08.11.35.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 08 Aug 2018 11:35:03 -0700 (PDT) From: Jim Wilson To: gdb-patches@sourceware.org Cc: Jim Wilson Subject: [PATCH 3/5] RISC-V: Add linux target support. Date: Wed, 8 Aug 2018 11:34:43 -0700 Message-Id: <20180808183443.25570-1-jimw@sifive.com> In-Reply-To: References: Add initial target support for riscv*-linux*. gdb/ * riscv-linux-tdep.c: New file. --- gdb/riscv-linux-tdep.c | 94 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+) create mode 100644 gdb/riscv-linux-tdep.c diff --git a/gdb/riscv-linux-tdep.c b/gdb/riscv-linux-tdep.c new file mode 100644 index 0000000000..47c2ab6d4f --- /dev/null +++ b/gdb/riscv-linux-tdep.c @@ -0,0 +1,94 @@ +/* Target-dependent code for GNU/Linux on RISC-V processors. + Copyright (C) 2018 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "defs.h" +#include "riscv-tdep.h" +#include "osabi.h" +#include "glibc-tdep.h" +#include "linux-tdep.h" +#include "solib-svr4.h" +#include "regset.h" + +/* Define the general register mapping. The kernel puts the PC at offset 0, + gdb puts it at offset 32. Register x0 is always 0 and can be ignored. + Registers x1 to x31 are in the same place. */ + +static const struct regcache_map_entry riscv_linux_gregmap[] = +{ + { 1, RISCV_PC_REGNUM, 0 }, + { 31, RISCV_RA_REGNUM, 0 }, /* x1 to x31 */ + { 0 } +}; + +/* Define the general register regset. */ + +static const struct regset riscv_linux_gregset = +{ + riscv_linux_gregmap, regcache_supply_regset, regcache_collect_regset +}; + +/* Define hook for core file support. */ + +static void +riscv_linux_iterate_over_regset_sections (struct gdbarch *gdbarch, + iterate_over_regset_sections_cb *cb, + void *cb_data, + const struct regcache *regcache) +{ + cb (".reg", (32 * riscv_isa_xlen (gdbarch)), + &riscv_linux_gregset, NULL, cb_data); + + /* TODO: Add FP register support. */ +} + +/* Initialize RISC-V Linux ABI info. */ + +static void +riscv_linux_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) +{ + linux_init_abi (info, gdbarch); + + set_gdbarch_software_single_step (gdbarch, riscv_software_single_step); + + set_solib_svr4_fetch_link_map_offsets (gdbarch, + (riscv_isa_xlen (gdbarch) == 4 + ? svr4_ilp32_fetch_link_map_offsets + : svr4_lp64_fetch_link_map_offsets)); + + /* GNU/Linux uses SVR4-style shared libraries. */ + set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); + + /* GNU/Linux uses the dynamic linker included in the GNU C Library. */ + set_gdbarch_skip_solib_resolver (gdbarch, glibc_skip_solib_resolver); + + /* Enable TLS support. */ + set_gdbarch_fetch_tls_load_module_address (gdbarch, + svr4_fetch_objfile_link_map); + + set_gdbarch_iterate_over_regset_sections + (gdbarch, riscv_linux_iterate_over_regset_sections); +} + +/* Initialize RISC-V Linux target support. */ + +void +_initialize_riscv_linux_tdep (void) +{ + gdbarch_register_osabi (bfd_arch_riscv, 0, GDB_OSABI_LINUX, + riscv_linux_init_abi); +}