From patchwork Sat May 2 00:17:49 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans-Peter Nilsson X-Patchwork-Id: 6531 Received: (qmail 17813 invoked by alias); 2 May 2015 00:17:57 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 17793 invoked by uid 89); 2 May 2015 00:17:57 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.1 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_NONE, SPF_PASS, T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-Spam-User: qpsmtpd, 2 recipients X-HELO: bes.se.axis.com Received: from bes.se.axis.com (HELO bes.se.axis.com) (195.60.68.10) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sat, 02 May 2015 00:17:55 +0000 Received: from localhost (localhost [127.0.0.1]) by bes.se.axis.com (Postfix) with ESMTP id 6DAD52E3F9; Sat, 2 May 2015 02:17:52 +0200 (CEST) Received: from bes.se.axis.com ([IPv6:::ffff:127.0.0.1]) by localhost (bes.se.axis.com [::ffff:127.0.0.1]) (amavisd-new, port 10024) with LMTP id yB895QFogu+M; Sat, 2 May 2015 02:17:50 +0200 (CEST) Received: from boulder.se.axis.com (boulder.se.axis.com [10.0.2.104]) by bes.se.axis.com (Postfix) with ESMTP id 898CC2E435; Sat, 2 May 2015 02:17:50 +0200 (CEST) Received: from boulder.se.axis.com (localhost [127.0.0.1]) by postfix.imss71 (Postfix) with ESMTP id 702771304; Sat, 2 May 2015 02:17:50 +0200 (CEST) Received: from thoth.se.axis.com (thoth.se.axis.com [10.0.2.173]) by boulder.se.axis.com (Postfix) with ESMTP id 61F2FF76; Sat, 2 May 2015 02:17:50 +0200 (CEST) Received: from ignucius.se.axis.com (ignucius.se.axis.com [10.88.21.50]) by thoth.se.axis.com (Postfix) with ESMTP id 5C92834005; Sat, 2 May 2015 02:17:50 +0200 (CEST) Received: from ignucius.se.axis.com (localhost [127.0.0.1]) by ignucius.se.axis.com (8.12.8p1/8.12.8/Debian-2woody1) with ESMTP id t420HnBc026229; Sat, 2 May 2015 02:17:50 +0200 Received: (from hp@localhost) by ignucius.se.axis.com (8.12.8p1/8.12.8/Debian-2woody1) id t420Hn09026225; Sat, 2 May 2015 02:17:49 +0200 Date: Sat, 2 May 2015 02:17:49 +0200 Message-Id: <201505020017.t420Hn09026225@ignucius.se.axis.com> From: Hans-Peter Nilsson To: gdb-patches@sourceware.org, binutils@sourceware.org CC: nickc@redhat.com Subject: Fix sim fallout from arm assembler complaining about symbols named as insns MIME-Version: 1.0 See commit 8b2d793ce5e and . I'm not completely sure this new gas warning is a good thing. I mean, symbols such as those below don't really interfere with the insn namespace, do they? Though, I'm somewhat sure that plain silencing the warning by adding (if supported) the new gas option -mno-warn-sym to the arm sim test-suite would be slightly uglier than the following; renaming the symbols. Either way, Nick (or anyone else), if prefer something else than what's below, don't let me get in the way of you fixing it to your liking. To wit, right now, the new symbol "sanity-check" causes failures for --target arm-eabi check-sim: Running /tmp/hpautotest-sim/src/sim/testsuite/sim/arm/allinsn.exp ... FAIL: xscale bl.cgs (assembling) Running /tmp/hpautotest-sim/src/sim/testsuite/sim/arm/iwmmxt/iwmmxt.exp ... FAIL: xscale tmia.cgs (assembling) FAIL: xscale tmiaph.cgs (assembling) FAIL: xscale waligni.cgs (assembling) FAIL: xscale wand.cgs (assembling) FAIL: xscale wandn.cgs (assembling) FAIL: xscale wmov.cgs (assembling) FAIL: xscale wor.cgs (assembling) FAIL: xscale wshufh.cgs (assembling) FAIL: xscale wxor.cgs (assembling) FAIL: xscale wzero.cgs (assembling) Running /tmp/hpautotest-sim/src/sim/testsuite/sim/arm/misc.exp ... Running /tmp/hpautotest-sim/src/sim/testsuite/sim/arm/thumb/allthumb.exp ... Running /tmp/hpautotest-sim/src/sim/testsuite/sim/arm/xscale/xscale.exp ... FAIL: xscale mia.cgs (assembling) FAIL: xscale miaph.cgs (assembling) sim.log: x/src/sim/testsuite/sim/arm/bl.cgs: Assembler messages: x/src/sim/testsuite/sim/arm/bl.cgs:8: Warning: [-mwarn-syms]: Symbol 'bl' matches an ARM instruction - is this intentional ? FAIL: xscale bl.cgs (assembling) (etc.) My suggestion follows. I'm holding off for a day or three. brgds, H-P diff --git a/sim/testsuite/sim/arm/ChangeLog b/sim/testsuite/sim/arm/ChangeLog index 1237d81..83dbd79 100644 --- a/sim/testsuite/sim/arm/ChangeLog +++ b/sim/testsuite/sim/arm/ChangeLog @@ -1,3 +1,19 @@ +2015-05-02 Hans-Peter Nilsson + + * bl.cgs (bl0): Rename from symbol colliding with insn name bl. + * iwmmxt/tmia.cgs (tmia0): Similar. + * iwmmxt/tmiaph.cgs (tmiaph0): Similar. + * iwmmxt/waligni.cgs (waligni0): Similar. + * iwmmxt/wand.cgs (wand0): Similar. + * iwmmxt/wandn.cgs (wandn0): Similar. + * iwmmxt/wmov.cgs (wmov0): Similar. + * iwmmxt/wor.cgs (wor0): Similar. + * iwmmxt/wshufh.cgs (wshuf0): Similar. + * iwmmxt/wxor.cgs (wxor0): Similar. + * iwmmxt/wzero.cgs (wzero0): Similar. + * xscale/mia.cgs (mia0): Similar. + * xscale/miaph.cgs (miaph0): Similar. + 2013-05-07 Jayant Sonar Kaushik Phatak diff --git a/sim/testsuite/sim/arm/bl.cgs b/sim/testsuite/sim/arm/bl.cgs index fbc7ef5..2655d3d 100644 --- a/sim/testsuite/sim/arm/bl.cgs +++ b/sim/testsuite/sim/arm/bl.cgs @@ -5,8 +5,8 @@ start - .global bl -bl: + .global bl0 +bl0: mvi_h_gr r14,0 bl bl2 bl1: diff --git a/sim/testsuite/sim/arm/iwmmxt/tmia.cgs b/sim/testsuite/sim/arm/iwmmxt/tmia.cgs index 0b0da66..8c6e0dd 100644 --- a/sim/testsuite/sim/arm/iwmmxt/tmia.cgs +++ b/sim/testsuite/sim/arm/iwmmxt/tmia.cgs @@ -6,8 +6,8 @@ start - .global tmia -tmia: + .global tmia0 +tmia0: # Enable access to CoProcessors 0 & 1 before # we attempt these instructions. diff --git a/sim/testsuite/sim/arm/iwmmxt/tmiaph.cgs b/sim/testsuite/sim/arm/iwmmxt/tmiaph.cgs index 3778b0a..820065a 100644 --- a/sim/testsuite/sim/arm/iwmmxt/tmiaph.cgs +++ b/sim/testsuite/sim/arm/iwmmxt/tmiaph.cgs @@ -6,8 +6,8 @@ start - .global tmiaph -tmiaph: + .global tmiaph0 +tmiaph0: # Enable access to CoProcessors 0 & 1 before # we attempt these instructions. diff --git a/sim/testsuite/sim/arm/iwmmxt/waligni.cgs b/sim/testsuite/sim/arm/iwmmxt/waligni.cgs index dc99dae..174e889 100644 --- a/sim/testsuite/sim/arm/iwmmxt/waligni.cgs +++ b/sim/testsuite/sim/arm/iwmmxt/waligni.cgs @@ -6,8 +6,8 @@ start - .global waligni -waligni: + .global waligni0 +waligni0: # Enable access to CoProcessors 0 & 1 before # we attempt these instructions. diff --git a/sim/testsuite/sim/arm/iwmmxt/wand.cgs b/sim/testsuite/sim/arm/iwmmxt/wand.cgs index 018383f..6ac45da 100644 --- a/sim/testsuite/sim/arm/iwmmxt/wand.cgs +++ b/sim/testsuite/sim/arm/iwmmxt/wand.cgs @@ -6,8 +6,8 @@ start - .global wand -wand: + .global wand0 +wand0: # Enable access to CoProcessors 0 & 1 before # we attempt these instructions. diff --git a/sim/testsuite/sim/arm/iwmmxt/wandn.cgs b/sim/testsuite/sim/arm/iwmmxt/wandn.cgs index f2c2305..907e3d0 100644 --- a/sim/testsuite/sim/arm/iwmmxt/wandn.cgs +++ b/sim/testsuite/sim/arm/iwmmxt/wandn.cgs @@ -6,8 +6,8 @@ start - .global wandn -wandn: + .global wandn0 +wandn0: # Enable access to CoProcessors 0 & 1 before # we attempt these instructions. diff --git a/sim/testsuite/sim/arm/iwmmxt/wmov.cgs b/sim/testsuite/sim/arm/iwmmxt/wmov.cgs index e86fed6..b7f88d1 100644 --- a/sim/testsuite/sim/arm/iwmmxt/wmov.cgs +++ b/sim/testsuite/sim/arm/iwmmxt/wmov.cgs @@ -6,8 +6,8 @@ start - .global wmov -wmov: + .global wmov0 +wmov0: # Enable access to CoProcessors 0 & 1 before # we attempt these instructions. diff --git a/sim/testsuite/sim/arm/iwmmxt/wor.cgs b/sim/testsuite/sim/arm/iwmmxt/wor.cgs index 48d5f53..6950beb 100644 --- a/sim/testsuite/sim/arm/iwmmxt/wor.cgs +++ b/sim/testsuite/sim/arm/iwmmxt/wor.cgs @@ -6,8 +6,8 @@ start - .global wor -wor: + .global wor0 +wor0: # Enable access to CoProcessors 0 & 1 before # we attempt these instructions. diff --git a/sim/testsuite/sim/arm/iwmmxt/wshufh.cgs b/sim/testsuite/sim/arm/iwmmxt/wshufh.cgs index d5cff1e..15b15bc 100644 --- a/sim/testsuite/sim/arm/iwmmxt/wshufh.cgs +++ b/sim/testsuite/sim/arm/iwmmxt/wshufh.cgs @@ -6,8 +6,8 @@ start - .global wshufh -wshufh: + .global wshufh0 +wshufh0: # Enable access to CoProcessors 0 & 1 before # we attempt these instructions. diff --git a/sim/testsuite/sim/arm/iwmmxt/wxor.cgs b/sim/testsuite/sim/arm/iwmmxt/wxor.cgs index 95e1fc8..922a30f 100644 --- a/sim/testsuite/sim/arm/iwmmxt/wxor.cgs +++ b/sim/testsuite/sim/arm/iwmmxt/wxor.cgs @@ -6,8 +6,8 @@ start - .global wxor -wxor: + .global wxor0 +wxor0: # Enable access to CoProcessors 0 & 1 before # we attempt these instructions. diff --git a/sim/testsuite/sim/arm/iwmmxt/wzero.cgs b/sim/testsuite/sim/arm/iwmmxt/wzero.cgs index 78fa7c5..52df3c8 100644 --- a/sim/testsuite/sim/arm/iwmmxt/wzero.cgs +++ b/sim/testsuite/sim/arm/iwmmxt/wzero.cgs @@ -6,8 +6,8 @@ start - .global wzero -wzero: + .global wzero0 +wzero0: # Enable access to CoProcessors 0 & 1 before # we attempt these instructions. diff --git a/sim/testsuite/sim/arm/xscale/mia.cgs b/sim/testsuite/sim/arm/xscale/mia.cgs index a3f729e..cfdc160 100644 --- a/sim/testsuite/sim/arm/xscale/mia.cgs +++ b/sim/testsuite/sim/arm/xscale/mia.cgs @@ -6,8 +6,8 @@ start - .global mia -mia: + .global mia0 +mia0: # Enable access to CoProcessors 0 & 1 before # we attempt these instructions. diff --git a/sim/testsuite/sim/arm/xscale/miaph.cgs b/sim/testsuite/sim/arm/xscale/miaph.cgs index 53fb201..c97b858 100644 --- a/sim/testsuite/sim/arm/xscale/miaph.cgs +++ b/sim/testsuite/sim/arm/xscale/miaph.cgs @@ -6,8 +6,8 @@ start - .global miaph -miaph: + .global miaph0 +miaph0: # Enable access to CoProcessors 0 & 1 before # we attempt these instructions.