From patchwork Fri Oct 13 14:34:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Marchi X-Patchwork-Id: 23545 Received: (qmail 46108 invoked by alias); 13 Oct 2017 14:35:16 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 45265 invoked by uid 89); 13 Oct 2017 14:35:14 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-24.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_PASS, UNSUBSCRIBE_BODY autolearn=ham version=3.3.2 spammy=Amount, 3999 X-HELO: sesbmg23.ericsson.net Received: from sesbmg23.ericsson.net (HELO sesbmg23.ericsson.net) (193.180.251.37) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 13 Oct 2017 14:35:07 +0000 Received: from ESESSHC020.ericsson.se (Unknown_Domain [153.88.183.78]) by sesbmg23.ericsson.net (Symantec Mail Security) with SMTP id EA.7D.03220.81FC0E95; Fri, 13 Oct 2017 16:35:04 +0200 (CEST) Received: from EUR02-AM5-obe.outbound.protection.outlook.com (153.88.183.145) by oa.msg.ericsson.com (153.88.183.78) with Microsoft SMTP Server (TLS) id 14.3.352.0; Fri, 13 Oct 2017 16:35:04 +0200 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=simon.marchi@ericsson.com; Received: from elxacz23q12.lan (192.222.251.162) by DBXPR07MB320.eurprd07.prod.outlook.com (2a01:111:e400:941d::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.77.5; Fri, 13 Oct 2017 14:35:00 +0000 From: Simon Marchi To: CC: Simon Marchi Subject: [PATCH] Create a displaced_step_closure class hierarchy Date: Fri, 13 Oct 2017 10:34:50 -0400 Message-ID: <1507905290-9405-1-git-send-email-simon.marchi@ericsson.com> MIME-Version: 1.0 X-ClientProxiedBy: BN6PR04CA0036.namprd04.prod.outlook.com (2603:10b6:405:3b::25) To DBXPR07MB320.eurprd07.prod.outlook.com (2a01:111:e400:941d::21) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 0c9e6fa4-259a-44d1-28a7-08d5124795d4 X-Microsoft-Antispam: UriScan:; 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Trying to xfree it from the common code (infrun.c) is a problem when we try to poison xfree for non-POD types. Because there can be multiple of these types in the same build, this patch makes a hierarchy of classes with a virtual destructor. When the common code deletes the object through a displaced_step_closure pointer, it will invoke the right destructor. The amd64 used a last-member array with a variable size. That doesn't work with new, so I changed it for an std::vector. Other architectures which used a simple byte buffer as a closure now use a shared buf_displaced_step_closure, a closure type that only contains a gdb::byte_vector. Reg-tested on the buildbot. gdb/ChangeLog: * infrun.h: Include common/byte-vector.h. (struct displaced_step_closure): New struct. (struct buf_displaced_step_closure): New struct. * infrun.c (displaced_step_closure::~displaced_step_closure): Provide default implementation. (displaced_step_clear): Deallocate step closure with delete. * aarch64-tdep.c (displaced_step_closure): Rename to ... (aarch64_displaced_step_closure): ... this, extend displaced_step_closure. (aarch64_displaced_step_data) : Change type to aarch64_displaced_step_closure. (aarch64_displaced_step_copy_insn): Adjust to type change, use unique_ptr. (aarch64_displaced_step_fixup): Add cast for displaced step closure. * amd64-tdep.c (displaced_step_closure): Rename to ... (amd64_displaced_step_closure): ... this, extend displaced_step_closure. : Change type to std::vector. : Remove. (fixup_riprel): Change type of DSC parameter, adjust to type change of insn_buf. (fixup_displaced_copy): Change type of DSC parameter. (amd64_displaced_step_copy_insn): Instantiate amd64_displaced_step_closure. (amd64_displaced_step_fixup): Add cast for closure type, adjust to type change of insn_buf. * arm-linux-tdep.c (arm_linux_cleanup_svc): Change type of parameter DSC. (arm_linux_copy_svc): Likewise. (cleanup_kernel_helper_return): Likewise. (arm_catch_kernel_helper_return): Likewise. (arm_linux_displaced_step_copy_insn): Instantiate arm_displaced_step_closure. * arm-tdep.c (arm_pc_is_thumb): Add cast for closure. (displaced_read_reg): Change type of parameter DSC. (branch_write_pc): Likewise. (load_write_pc): Likewise. (alu_write_pc): Likewise. (displaced_write_reg): Likewise. (arm_copy_unmodified): Likewise. (thumb_copy_unmodified_32bit): Likewise. (thumb_copy_unmodified_16bit): Likewise. (cleanup_preload): Likewise. (install_preload): Likewise. (arm_copy_preload): Likewise. (thumb2_copy_preload): Likewise. (install_preload_reg): Likewise. (arm_copy_preload_reg): Likewise. (cleanup_copro_load_store): Likewise. (install_copro_load_store): Likewise. (arm_copy_copro_load_store) Likewise. (thumb2_copy_copro_load_store): Likewise. (cleanup_branch): Likewise. (install_b_bl_blx): Likewise. (arm_copy_b_bl_blx): Likewise. (thumb2_copy_b_bl_blx): Likewise. (thumb_copy_b): Likewise. (install_bx_blx_reg): Likewise. (arm_copy_bx_blx_reg): Likewise. (thumb_copy_bx_blx_reg): Likewise. (cleanup_alu_imm): Likewise. (arm_copy_alu_imm): Likewise. (thumb2_copy_alu_imm): Likewise. (cleanup_alu_reg): Likewise. (install_alu_reg): Likewise. (arm_copy_alu_reg): Likewise. (thumb_copy_alu_reg): Likewise. (cleanup_alu_shifted_reg): Likewise. (install_alu_shifted_reg): Likewise. (arm_copy_alu_shifted_reg): Likewise. (cleanup_load): Likewise. (cleanup_store): Likewise. (arm_copy_extra_ld_st): Likewise. (install_load_store): Likewise. (thumb2_copy_load_literal): Likewise. (thumb2_copy_load_reg_imm): Likewise. (arm_copy_ldr_str_ldrb_strb): Likewise. (cleanup_block_load_all): Likewise. (cleanup_block_store_pc): Likewise. (cleanup_block_load_pc): Likewise. (arm_copy_block_xfer): Likewise. (thumb2_copy_block_xfer): Likewise. (cleanup_svc): Likewise. (install_svc): Likewise. (arm_copy_svc): Likewise. (thumb_copy_svc): Likewise. (arm_copy_undef): Likewise. (thumb_32bit_copy_undef): Likewise. (arm_copy_unpred): Likewise. (arm_decode_misc_memhint_neon): Likewise. (arm_decode_unconditional): Likewise. (arm_decode_miscellaneous): Likewise. (arm_decode_dp_misc): Likewise. (arm_decode_ld_st_word_ubyte): Likewise. (arm_decode_media): Likewise. (arm_decode_b_bl_ldmstm): Likewise. (arm_decode_ext_reg_ld_st): Likewise. (thumb2_decode_dp_shift_reg): Likewise. (thumb2_decode_ext_reg_ld_st): Likewise. (arm_decode_svc_copro): Likewise. (thumb2_decode_svc_copro): Likewise. (install_pc_relative): Likewise. (thumb_copy_pc_relative_16bit): Likewise. (thumb_decode_pc_relative_16bit): Likewise. (thumb_copy_pc_relative_32bit): Likewise. (thumb_copy_16bit_ldr_literal): Likewise. (thumb_copy_cbnz_cbz): Likewise. (thumb2_copy_table_branch): Likewise. (cleanup_pop_pc_16bit_all): Likewise. (thumb_copy_pop_pc_16bit): Likewise. (thumb_process_displaced_16bit_insn): Likewise. (decode_thumb_32bit_ld_mem_hints): Likewise. (thumb_process_displaced_32bit_insn): Likewise. (thumb_process_displaced_insn): Likewise. (arm_process_displaced_insn): Likewise. (arm_displaced_init_closure): Likewise. (arm_displaced_step_fixup): Add cast for closure. * arm-tdep.h: Include infrun.h. (displaced_step_closure): Rename to ... (arm_displaced_step_closure): ... this, extend displaced_step_closure. : Change type of parameter DSC. : Likewise. (arm_process_displaced_insn): Likewise. (arm_displaced_init_closure): Likewise. (displaced_read_reg): Likewise. (displaced_write_reg): Likewise. * i386-linux-tdep.c (i386_linux_displaced_step_copy_insn): Adjust. * i386-tdep.h: Include infrun.h. (i386_displaced_step_closure): New typedef. * i386-tdep.c (i386_displaced_step_copy_insn): Use i386_displaced_step_closure. (i386_displaced_step_fixup): Adjust. * rs6000-tdep.c (ppc_displaced_step_closure): New typedef. (ppc_displaced_step_copy_insn): Use ppc_displaced_step_closure and unique_ptr. (ppc_displaced_step_fixup): Adjust. * s390-linux-tdep.c (s390_displaced_step_closure): New typedef. (s390_displaced_step_copy_insn): Use s390_displaced_step_closure and unique_ptr. (s390_displaced_step_fixup): Adjust. --- gdb/aarch64-tdep.c | 21 +++--- gdb/amd64-tdep.c | 38 ++++++----- gdb/arm-linux-tdep.c | 10 +-- gdb/arm-tdep.c | 173 +++++++++++++++++++++++++------------------------- gdb/arm-tdep.h | 15 +++-- gdb/i386-linux-tdep.c | 14 ++-- gdb/i386-tdep.c | 12 ++-- gdb/i386-tdep.h | 4 ++ gdb/infrun.c | 8 ++- gdb/infrun.h | 19 ++++++ gdb/rs6000-tdep.c | 19 +++--- gdb/s390-linux-tdep.c | 18 ++++-- 12 files changed, 194 insertions(+), 157 deletions(-) diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c index a40dc69..cbab1a5 100644 --- a/gdb/aarch64-tdep.c +++ b/gdb/aarch64-tdep.c @@ -2488,14 +2488,14 @@ aarch64_software_single_step (struct regcache *regcache) return next_pcs; } -struct displaced_step_closure +struct aarch64_displaced_step_closure : public displaced_step_closure { /* It is true when condition instruction, such as B.CON, TBZ, etc, is being displaced stepping. */ - int cond; + int cond = 0; /* PC adjustment offset after displaced stepping. */ - int32_t pc_adjust; + int32_t pc_adjust = 0; }; /* Data when visiting instructions for displaced stepping. */ @@ -2513,7 +2513,7 @@ struct aarch64_displaced_step_data /* Registers when doing displaced stepping. */ struct regcache *regs; - struct displaced_step_closure *dsc; + aarch64_displaced_step_closure *dsc; }; /* Implementation of aarch64_insn_visitor method "b". */ @@ -2727,7 +2727,6 @@ aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to, struct regcache *regs) { - struct displaced_step_closure *dsc = NULL; enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); uint32_t insn = read_memory_unsigned_integer (from, 4, byte_order_for_code); struct aarch64_displaced_step_data dsd; @@ -2743,11 +2742,12 @@ aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch, return NULL; } - dsc = XCNEW (struct displaced_step_closure); + std::unique_ptr dsc + (new aarch64_displaced_step_closure); dsd.base.insn_addr = from; dsd.new_addr = to; dsd.regs = regs; - dsd.dsc = dsc; + dsd.dsc = dsc.get (); dsd.insn_count = 0; aarch64_relocate_instruction (insn, &visitor, (struct aarch64_insn_data *) &dsd); @@ -2773,21 +2773,22 @@ aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch, } else { - xfree (dsc); dsc = NULL; } - return dsc; + return dsc.release (); } /* Implement the "displaced_step_fixup" gdbarch method. */ void aarch64_displaced_step_fixup (struct gdbarch *gdbarch, - struct displaced_step_closure *dsc, + struct displaced_step_closure *dsc_, CORE_ADDR from, CORE_ADDR to, struct regcache *regs) { + aarch64_displaced_step_closure *dsc = (aarch64_displaced_step_closure *) dsc_; + if (dsc->cond) { ULONGEST pc; diff --git a/gdb/amd64-tdep.c b/gdb/amd64-tdep.c index e56c388..08a9cae 100644 --- a/gdb/amd64-tdep.c +++ b/gdb/amd64-tdep.c @@ -46,6 +46,7 @@ #include "producer.h" #include "ax.h" #include "ax-gdb.h" +#include "common/byte-vector.h" /* Note that the AMD64 architecture was previously known as x86-64. The latter is (forever) engraved into the canonical system name as @@ -1047,22 +1048,22 @@ struct amd64_insn gdb_byte *raw_insn; }; -struct displaced_step_closure +struct amd64_displaced_step_closure : public displaced_step_closure { + amd64_displaced_step_closure (int insn_buf_len) + : insn_buf (insn_buf_len, 0) + {} + /* For rip-relative insns, saved copy of the reg we use instead of %rip. */ - int tmp_used; + int tmp_used = 0; int tmp_regno; ULONGEST tmp_save; /* Details of the instruction. */ struct amd64_insn insn_details; - /* Amount of space allocated to insn_buf. */ - int max_len; - - /* The possibly modified insn. - This is a variable-length field. */ - gdb_byte insn_buf[1]; + /* The possibly modified insn. */ + gdb::byte_vector insn_buf; }; /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with @@ -1303,7 +1304,7 @@ amd64_get_insn_details (gdb_byte *insn, struct amd64_insn *details) We set base = pc + insn_length so we can leave disp unchanged. */ static void -fixup_riprel (struct gdbarch *gdbarch, struct displaced_step_closure *dsc, +fixup_riprel (struct gdbarch *gdbarch, amd64_displaced_step_closure *dsc, CORE_ADDR from, CORE_ADDR to, struct regcache *regs) { const struct amd64_insn *insn_details = &dsc->insn_details; @@ -1318,8 +1319,8 @@ fixup_riprel (struct gdbarch *gdbarch, struct displaced_step_closure *dsc, ++insn; /* Compute the rip-relative address. */ - insn_length = gdb_buffered_insn_length (gdbarch, dsc->insn_buf, - dsc->max_len, from); + insn_length = gdb_buffered_insn_length (gdbarch, dsc->insn_buf.data (), + dsc->insn_buf.size (), from); rip_base = from + insn_length; /* We need a register to hold the address. @@ -1353,7 +1354,7 @@ fixup_riprel (struct gdbarch *gdbarch, struct displaced_step_closure *dsc, static void fixup_displaced_copy (struct gdbarch *gdbarch, - struct displaced_step_closure *dsc, + amd64_displaced_step_closure *dsc, CORE_ADDR from, CORE_ADDR to, struct regcache *regs) { const struct amd64_insn *details = &dsc->insn_details; @@ -1380,15 +1381,11 @@ amd64_displaced_step_copy_insn (struct gdbarch *gdbarch, /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to continually watch for running off the end of the buffer. */ int fixup_sentinel_space = len; - struct displaced_step_closure *dsc - = ((struct displaced_step_closure *) - xmalloc (sizeof (*dsc) + len + fixup_sentinel_space)); + amd64_displaced_step_closure *dsc + = new amd64_displaced_step_closure (len + fixup_sentinel_space); gdb_byte *buf = &dsc->insn_buf[0]; struct amd64_insn *details = &dsc->insn_details; - dsc->tmp_used = 0; - dsc->max_len = len + fixup_sentinel_space; - read_memory (from, buf, len); /* Set up the sentinel space so we don't have to worry about running @@ -1583,14 +1580,15 @@ amd64_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr) void amd64_displaced_step_fixup (struct gdbarch *gdbarch, - struct displaced_step_closure *dsc, + struct displaced_step_closure *dsc_, CORE_ADDR from, CORE_ADDR to, struct regcache *regs) { + amd64_displaced_step_closure *dsc = (amd64_displaced_step_closure *) dsc_; enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); /* The offset we applied to the instruction's address. */ ULONGEST insn_offset = to - from; - gdb_byte *insn = dsc->insn_buf; + gdb_byte *insn = dsc->insn_buf.data (); const struct amd64_insn *insn_details = &dsc->insn_details; if (debug_displaced) diff --git a/gdb/arm-linux-tdep.c b/gdb/arm-linux-tdep.c index 056c1b9..4d1d890 100644 --- a/gdb/arm-linux-tdep.c +++ b/gdb/arm-linux-tdep.c @@ -950,7 +950,7 @@ arm_linux_software_single_step (struct regcache *regcache) static void arm_linux_cleanup_svc (struct gdbarch *gdbarch, struct regcache *regs, - struct displaced_step_closure *dsc) + arm_displaced_step_closure *dsc) { ULONGEST apparent_pc; int within_scratch; @@ -978,7 +978,7 @@ arm_linux_cleanup_svc (struct gdbarch *gdbarch, static int arm_linux_copy_svc (struct gdbarch *gdbarch, struct regcache *regs, - struct displaced_step_closure *dsc) + arm_displaced_step_closure *dsc) { CORE_ADDR return_to = 0; @@ -1069,7 +1069,7 @@ arm_linux_copy_svc (struct gdbarch *gdbarch, struct regcache *regs, static void cleanup_kernel_helper_return (struct gdbarch *gdbarch, struct regcache *regs, - struct displaced_step_closure *dsc) + arm_displaced_step_closure *dsc) { displaced_write_reg (regs, dsc, ARM_LR_REGNUM, dsc->tmp[0], CANNOT_WRITE_PC); displaced_write_reg (regs, dsc, ARM_PC_REGNUM, dsc->tmp[0], BRANCH_WRITE_PC); @@ -1078,7 +1078,7 @@ cleanup_kernel_helper_return (struct gdbarch *gdbarch, static void arm_catch_kernel_helper_return (struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to, struct regcache *regs, - struct displaced_step_closure *dsc) + arm_displaced_step_closure *dsc) { enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); @@ -1112,7 +1112,7 @@ arm_linux_displaced_step_copy_insn (struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to, struct regcache *regs) { - struct displaced_step_closure *dsc = XNEW (struct displaced_step_closure); + arm_displaced_step_closure *dsc = new arm_displaced_step_closure; /* Detect when we enter an (inaccessible by GDB) Linux kernel helper, and stop at the return location. */ diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 960696d..fc6197d 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -399,8 +399,9 @@ arm_pc_is_thumb (struct gdbarch *gdbarch, CORE_ADDR memaddr) { struct bound_minimal_symbol sym; char type; - struct displaced_step_closure* dsc - = get_displaced_step_closure_by_addr(memaddr); + arm_displaced_step_closure *dsc + = ((arm_displaced_step_closure * ) + get_displaced_step_closure_by_addr (memaddr)); /* If checking the mode of displaced instruction in copy area, the mode should be determined by instruction on the original address. */ @@ -4413,7 +4414,7 @@ arm_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) location. */ ULONGEST -displaced_read_reg (struct regcache *regs, struct displaced_step_closure *dsc, +displaced_read_reg (struct regcache *regs, arm_displaced_step_closure *dsc, int regno) { ULONGEST ret; @@ -4461,7 +4462,7 @@ displaced_in_arm_mode (struct regcache *regs) /* Write to the PC as from a branch instruction. */ static void -branch_write_pc (struct regcache *regs, struct displaced_step_closure *dsc, +branch_write_pc (struct regcache *regs, arm_displaced_step_closure *dsc, ULONGEST val) { if (!dsc->is_thumb) @@ -4507,7 +4508,7 @@ bx_write_pc (struct regcache *regs, ULONGEST val) /* Write to the PC as if from a load instruction. */ static void -load_write_pc (struct regcache *regs, struct displaced_step_closure *dsc, +load_write_pc (struct regcache *regs, arm_displaced_step_closure *dsc, ULONGEST val) { if (DISPLACED_STEPPING_ARCH_VERSION >= 5) @@ -4519,7 +4520,7 @@ load_write_pc (struct regcache *regs, struct displaced_step_closure *dsc, /* Write to the PC as if from an ALU instruction. */ static void -alu_write_pc (struct regcache *regs, struct displaced_step_closure *dsc, +alu_write_pc (struct regcache *regs, arm_displaced_step_closure *dsc, ULONGEST val) { if (DISPLACED_STEPPING_ARCH_VERSION >= 7 && !dsc->is_thumb) @@ -4533,7 +4534,7 @@ alu_write_pc (struct regcache *regs, struct displaced_step_closure *dsc, this is controlled by the WRITE_PC argument. */ void -displaced_write_reg (struct regcache *regs, struct displaced_step_closure *dsc, +displaced_write_reg (struct regcache *regs, arm_displaced_step_closure *dsc, int regno, ULONGEST val, enum pc_write_style write_pc) { if (regno == ARM_PC_REGNUM) @@ -4617,7 +4618,7 @@ insn_references_pc (uint32_t insn, uint32_t bitmask) static int arm_copy_unmodified (struct gdbarch *gdbarch, uint32_t insn, - const char *iname, struct displaced_step_closure *dsc) + const char *iname, arm_displaced_step_closure *dsc) { if (debug_displaced) fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.8lx, " @@ -4632,7 +4633,7 @@ arm_copy_unmodified (struct gdbarch *gdbarch, uint32_t insn, static int thumb_copy_unmodified_32bit (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, const char *iname, - struct displaced_step_closure *dsc) + arm_displaced_step_closure *dsc) { if (debug_displaced) fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x %.4x, " @@ -4651,7 +4652,7 @@ thumb_copy_unmodified_32bit (struct gdbarch *gdbarch, uint16_t insn1, static int thumb_copy_unmodified_16bit (struct gdbarch *gdbarch, uint16_t insn, const char *iname, - struct displaced_step_closure *dsc) + arm_displaced_step_closure *dsc) { if (debug_displaced) fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x, " @@ -4667,7 +4668,7 @@ thumb_copy_unmodified_16bit (struct gdbarch *gdbarch, uint16_t insn, static void cleanup_preload (struct gdbarch *gdbarch, - struct regcache *regs, struct displaced_step_closure *dsc) + struct regcache *regs, arm_displaced_step_closure *dsc) { displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); if (!dsc->u.preload.immed) @@ -4676,7 +4677,7 @@ cleanup_preload (struct gdbarch *gdbarch, static void install_preload (struct gdbarch *gdbarch, struct regcache *regs, - struct displaced_step_closure *dsc, unsigned int rn) + arm_displaced_step_closure *dsc, unsigned int rn) { ULONGEST rn_val; /* Preload instructions: @@ -4695,7 +4696,7 @@ install_preload (struct gdbarch *gdbarch, struct regcache *regs, static int arm_copy_preload (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, - struct displaced_step_closure *dsc) + arm_displaced_step_closure *dsc) { unsigned int rn = bits (insn, 16, 19); @@ -4715,7 +4716,7 @@ arm_copy_preload (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, static int thumb2_copy_preload (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, - struct regcache *regs, struct displaced_step_closure *dsc) + struct regcache *regs, arm_displaced_step_closure *dsc) { unsigned int rn = bits (insn1, 0, 3); unsigned int u_bit = bit (insn1, 7); @@ -4765,7 +4766,7 @@ thumb2_copy_preload (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, static void install_preload_reg(struct gdbarch *gdbarch, struct regcache *regs, - struct displaced_step_closure *dsc, unsigned int rn, + arm_displaced_step_closure *dsc, unsigned int rn, unsigned int rm) { ULONGEST rn_val, rm_val; @@ -4790,7 +4791,7 @@ install_preload_reg(struct gdbarch *gdbarch, struct regcache *regs, static int arm_copy_preload_reg (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, - struct displaced_step_closure *dsc) + arm_displaced_step_closure *dsc) { unsigned int rn = bits (insn, 16, 19); unsigned int rm = bits (insn, 0, 3); @@ -4814,7 +4815,7 @@ arm_copy_preload_reg (struct gdbarch *gdbarch, uint32_t insn, static void cleanup_copro_load_store (struct gdbarch *gdbarch, struct regcache *regs, - struct displaced_step_closure *dsc) + arm_displaced_step_closure *dsc) { ULONGEST rn_val = displaced_read_reg (regs, dsc, 0); @@ -4826,7 +4827,7 @@ cleanup_copro_load_store (struct gdbarch *gdbarch, static void install_copro_load_store (struct gdbarch *gdbarch, struct regcache *regs, - struct displaced_step_closure *dsc, + arm_displaced_step_closure *dsc, int writeback, unsigned int rn) { ULONGEST rn_val; @@ -4854,7 +4855,7 @@ install_copro_load_store (struct gdbarch *gdbarch, struct regcache *regs, static int arm_copy_copro_load_store (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, - struct displaced_step_closure *dsc) + arm_displaced_step_closure *dsc) { unsigned int rn = bits (insn, 16, 19); @@ -4875,7 +4876,7 @@ arm_copy_copro_load_store (struct gdbarch *gdbarch, uint32_t insn, static int thumb2_copy_copro_load_store (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, - struct displaced_step_closure *dsc) + arm_displaced_step_closure *dsc) { unsigned int rn = bits (insn1, 0, 3); @@ -4903,7 +4904,7 @@ thumb2_copy_copro_load_store (struct gdbarch *gdbarch, uint16_t insn1, static void cleanup_branch (struct gdbarch *gdbarch, struct regcache *regs, - struct displaced_step_closure *dsc) + arm_displaced_step_closure *dsc) { uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM); int branch_taken = condition_true (dsc->u.branch.cond, status); @@ -4934,7 +4935,7 @@ cleanup_branch (struct gdbarch *gdbarch, struct regcache *regs, static void install_b_bl_blx (struct gdbarch *gdbarch, struct regcache *regs, - struct displaced_step_closure *dsc, + arm_displaced_step_closure *dsc, unsigned int cond, int exchange, int link, long offset) { /* Implement "BL