From patchwork Thu Dec 1 11:16:40 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yao Qi X-Patchwork-Id: 18096 Received: (qmail 60150 invoked by alias); 1 Dec 2016 11:17:01 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 60128 invoked by uid 89); 1 Dec 2016 11:17:01 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.5 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM, SPF_PASS autolearn=no version=3.3.2 spammy=H*m:19457 X-HELO: mail-pg0-f68.google.com Received: from mail-pg0-f68.google.com (HELO mail-pg0-f68.google.com) (74.125.83.68) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 01 Dec 2016 11:16:52 +0000 Received: by mail-pg0-f68.google.com with SMTP id x23so4372937pgx.3 for ; Thu, 01 Dec 2016 03:16:51 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=a8bAIRmzcaaJtlf4+EUprQOZpz2Pc7ZxhdPrE/SiMm4=; b=lDQyjM2VgjsvjvMpSphtONVhQe+QXQGqyGwYEof9slhOQ0aXvvscDthuMXACQ41/tl BmhP0s3nofFnhUCmFqc0v/XmWLlMqPhpsrcPYlYQxgfdgArBMcPqV+z1Xd5F1nkvZk3i HbLceB8xawU5h8R664P7rRcNtEu+3O6lDQqd+oZFDxHhpz+O7CAif0BlOBTst8c0Ua9v OarGV5vgD5spRReJW5XYzuurj/AGKlJQAHnLNMwRnYigryhIWZGTkH7jD3tsDGGPOcAs 0De9Pk5IFQoKcQIk0/O3rdYxLKckkjV6zYODqGvU4lAz4/AOnJOka93ttFaX8z2KATPi Pv0Q== X-Gm-Message-State: AKaTC01HlQohCE/72EElLPi5jNDN7KlGzncU+oQvEpylq2gcnGP0Ha/H+5iMSiN+0AGiSw== X-Received: by 10.99.67.7 with SMTP id q7mr67922746pga.45.1480591010324; Thu, 01 Dec 2016 03:16:50 -0800 (PST) Received: from E107787-LIN.cambridge.arm.com (gcc1-power7.osuosl.org. [140.211.15.137]) by smtp.gmail.com with ESMTPSA id y200sm104956413pfb.16.2016.12.01.03.16.49 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 01 Dec 2016 03:16:49 -0800 (PST) From: Yao Qi X-Google-Original-From: Yao Qi To: gdb-patches@sourceware.org Subject: [PATCH 2/2 v2] [AArch64] Recognize STR instruction in prologue Date: Thu, 1 Dec 2016 11:16:40 +0000 Message-Id: <1480591000-19457-2-git-send-email-yao.qi@linaro.org> In-Reply-To: <1480591000-19457-1-git-send-email-yao.qi@linaro.org> References: <1480428758-2481-1-git-send-email-yao.qi@linaro.org> <1480591000-19457-1-git-send-email-yao.qi@linaro.org> X-IsSubscribed: yes This patch teaches GDB AArch64 backend to recognize STR instructions in prologue, like 'str x19, [sp, #-48]!' or 'str w0, [sp, #44]'. The unit test is added too. gdb: 2016-11-28 Yao Qi Pedro Alves * aarch64-tdep.c (aarch64_analyze_prologue): Recognize STR instruction. (aarch64_analyze_prologue_test): More tests. --- gdb/aarch64-tdep.c | 75 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c index c8a69a8..45dd5e4 100644 --- a/gdb/aarch64-tdep.c +++ b/gdb/aarch64-tdep.c @@ -395,6 +395,35 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch, regs[rn] = pv_add_constant (regs[rn], imm); } + else if ((inst.opcode->iclass == ldst_imm9 /* Signed immediate. */ + || (inst.opcode->iclass == ldst_pos /* Unsigned immediate. */ + && (inst.opcode->op == OP_STR_POS + || inst.opcode->op == OP_STRF_POS))) + && inst.operands[1].addr.base_regno == AARCH64_SP_REGNUM + && strcmp ("str", inst.opcode->name) == 0) + { + /* STR (immediate) */ + unsigned int rt = inst.operands[0].reg.regno; + int32_t imm = inst.operands[1].addr.offset.imm; + unsigned rn = inst.operands[1].addr.base_regno; + int is64 + = (aarch64_get_qualifier_esize (inst.operands[0].qualifier) == 8); + gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt + || inst.operands[0].type == AARCH64_OPND_Ft); + + if (inst.operands[0].type == AARCH64_OPND_Ft) + { + /* Only bottom 64-bit of each V register (D register) need + to be preserved. */ + gdb_assert (inst.operands[0].qualifier == AARCH64_OPND_QLF_S_D); + rt += AARCH64_X_REGISTER_COUNT; + } + + pv_area_store (stack, pv_add_constant (regs[rn], imm), + is64 ? 8 : 4, regs[rt]); + if (inst.operands[1].addr.writeback) + regs[rn] = pv_add_constant (regs[rn], imm); + } else if (inst.opcode->iclass == testbranch) { /* Stop analysis on branch. */ @@ -546,6 +575,52 @@ aarch64_analyze_prologue_test (void) == -1); } } + + /* Test a prologue in which STR is used and frame pointer is not + used. */ + { + struct aarch64_prologue_cache cache; + cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch); + + const uint32_t insns[] = { + 0xf81d0ff3, /* str x19, [sp, #-48]! */ + 0xb9002fe0, /* str w0, [sp, #44] */ + 0xf90013e1, /* str x1, [sp, #32]*/ + 0xfd000fe0, /* str d0, [sp, #24] */ + 0xaa0203f3, /* mov x19, x2 */ + 0xf94013e0, /* ldr x0, [sp, #32] */ + }; + instruction_reader_test reader (insns); + + CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader); + + SELF_CHECK (end == 4 * 5); + + SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM); + SELF_CHECK (cache.framesize == 48); + + for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++) + { + if (i == 1) + SELF_CHECK (cache.saved_regs[i].addr == -16); + else if (i == 19) + SELF_CHECK (cache.saved_regs[i].addr == -48); + else + SELF_CHECK (cache.saved_regs[i].addr == -1); + } + + for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++) + { + int regnum = gdbarch_num_regs (gdbarch); + + if (i == 0) + SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr + == -24); + else + SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr + == -1); + } + } } } #endif /* GDB_SELF_TEST */