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j1sm20408211wjm.26.2016.11.20.09.39.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 20 Nov 2016 09:40:40 -0800 (PST) From: Ambrogino Modigliani X-Google-Original-From: Ambrogino Modigliani To: gdb-patches@sourceware.org, pedro_alves@portugalmail.pt, ambrogino.modigliani@gmail.com, ambrogino.modigliani@mail.com Subject: [PATCH 09/23] Fix spelling mistakes in comments in Assembler files Date: Sun, 20 Nov 2016 18:38:04 +0100 Message-Id: <1479663498-30295-10-git-send-email-ambrogino.modigliani@mail.com> In-Reply-To: <1479663498-30295-1-git-send-email-ambrogino.modigliani@mail.com> References: <1479663498-30295-1-git-send-email-ambrogino.modigliani@mail.com> gas/testsuite/ChangeLog: * gas/testsuite/gas/arm/local_function.d: Fix spelling in comments. * gas/testsuite/gas/arm/req.s: Fix spelling in comments. * gas/testsuite/gas/arm/vfp1.s: Fix spelling in comments. * gas/testsuite/gas/arm/vfp1_t2.s: Fix spelling in comments. * gas/testsuite/gas/arm/vfp1xD.s: Fix spelling in comments. * gas/testsuite/gas/arm/vfp1xD_t2.s: Fix spelling in comments. * gas/testsuite/gas/mcore/allinsn.s: Fix spelling in comments. * gas/testsuite/gas/mips/24k-triple-stores-5.s: Fix spelling in comments. * gas/testsuite/gas/mips/delay.d: Fix spelling in comments. * gas/testsuite/gas/mips/nodelay.d: Fix spelling in comments. * gas/testsuite/gas/mips/r5900-full.s: Fix spelling in comments. * gas/testsuite/gas/mips/r5900.s: Fix spelling in comments. * gdb/testsuite/gdb.dwarf2/fission-reread.S: Fix spelling in comments. * gdb/testsuite/gdb.dwarf2/pr13961.S: Fix spelling in comments. ld/testsuite/ChangeLog: * ld/testsuite/ld-arm/stm32l4xx-fix-all.s: Fix spelling in comments. * ld/testsuite/ld-arm/thumb2-b-interwork.s: Fix spelling in comments. * ld/testsuite/ld-arm/thumb2-bl.s: Fix spelling in comments. * ld/testsuite/ld-s390/tlspic1.s: Fix spelling in comments. * ld/testsuite/ld-s390/tlspic1_64.s: Fix spelling in comments. * ld/testsuite/ld-scripts/section-match-1.d: Fix spelling in comments. sim/testsuite/ChangeLog: * sim/testsuite/d10v-elf/t-macros.i: Fix spelling in comments. * sim/testsuite/sim/bfin/divq.s: Fix spelling in comments. * sim/testsuite/sim/bfin/se_illegalcombination.S: Fix spelling in comments. * sim/testsuite/sim/bfin/se_undefinedinstruction1.S: Fix spelling in comments. * sim/testsuite/sim/bfin/se_undefinedinstruction2.S: Fix spelling in comments. * sim/testsuite/sim/fr30/addsp.cgs: Fix spelling in comments. * sim/testsuite/sim/fr30/bc.cgs: Fix spelling in comments. * sim/testsuite/sim/fr30/beq.cgs: Fix spelling in comments. * sim/testsuite/sim/fr30/bge.cgs: Fix spelling in comments. * sim/testsuite/sim/fr30/bgt.cgs: Fix spelling in comments. * sim/testsuite/sim/fr30/bhi.cgs: Fix spelling in comments. * sim/testsuite/sim/fr30/ble.cgs: Fix spelling in comments. * sim/testsuite/sim/fr30/bls.cgs: Fix spelling in comments. * sim/testsuite/sim/fr30/blt.cgs: Fix spelling in comments. * sim/testsuite/sim/fr30/bn.cgs: Fix spelling in comments. * sim/testsuite/sim/fr30/bnc.cgs: Fix spelling in comments. * sim/testsuite/sim/fr30/bne.cgs: Fix spelling in comments. * sim/testsuite/sim/fr30/bno.cgs: Fix spelling in comments. * sim/testsuite/sim/fr30/bnv.cgs: Fix spelling in comments. * sim/testsuite/sim/fr30/bp.cgs: Fix spelling in comments. * sim/testsuite/sim/fr30/bra.cgs: Fix spelling in comments. * sim/testsuite/sim/fr30/bv.cgs: Fix spelling in comments. * sim/testsuite/sim/fr30/copld.cgs: Fix spelling in comments. * sim/testsuite/sim/fr30/copop.cgs: Fix spelling in comments. * sim/testsuite/sim/fr30/copst.cgs: Fix spelling in comments. * sim/testsuite/sim/fr30/copsv.cgs: Fix spelling in comments. * sim/testsuite/sim/fr30/enter.cgs: Fix spelling in comments. * sim/testsuite/sim/fr30/extsb.cgs: Fix spelling in comments. * sim/testsuite/sim/fr30/extsh.cgs: Fix spelling in comments. * sim/testsuite/sim/fr30/extub.cgs: Fix spelling in comments. * sim/testsuite/sim/fr30/extuh.cgs: Fix spelling in comments. * sim/testsuite/sim/fr30/ldres.cgs: Fix spelling in comments. * sim/testsuite/sim/fr30/leave.cgs: Fix spelling in comments. * sim/testsuite/sim/fr30/nop.cgs: Fix spelling in comments. * sim/testsuite/sim/fr30/stres.cgs: Fix spelling in comments. * sim/testsuite/sim/fr30/xchb.cgs: Fix spelling in comments. * sim/testsuite/sim/h8300/ldc.s: Fix spelling in comments. * sim/testsuite/sim/h8300/stc.s: Fix spelling in comments. * sim/testsuite/sim/mips/hilo-hazard-3.s: Fix spelling in comments. * sim/testsuite/sim/mips/hilo-hazard-4.s: Fix spelling in comments. * sim/testsuite/sim/sh/fipr.s: Fix spelling in comments. zlib`/ChangeLog: * zlib/contrib/inflate86/inffast.S: Fix spelling in comments. --- gas/testsuite/gas/arm/local_function.d | 2 +- gas/testsuite/gas/arm/req.s | 2 +- gas/testsuite/gas/arm/vfp1.s | 2 +- gas/testsuite/gas/arm/vfp1_t2.s | 2 +- gas/testsuite/gas/arm/vfp1xD.s | 2 +- gas/testsuite/gas/arm/vfp1xD_t2.s | 2 +- gas/testsuite/gas/mcore/allinsn.s | 4 +- gas/testsuite/gas/mips/24k-triple-stores-5.s | 2 +- gas/testsuite/gas/mips/delay.d | 2 +- gas/testsuite/gas/mips/nodelay.d | 2 +- gas/testsuite/gas/mips/r5900-full.s | 2 +- gas/testsuite/gas/mips/r5900.s | 2 +- gdb/testsuite/gdb.dwarf2/fission-reread.S | 2 +- gdb/testsuite/gdb.dwarf2/pr13961.S | 4 +- ld/testsuite/ld-arm/stm32l4xx-fix-all.s | 4 +- ld/testsuite/ld-arm/thumb2-b-interwork.s | 2 +- ld/testsuite/ld-arm/thumb2-bl.s | 2 +- ld/testsuite/ld-s390/tlspic1.s | 4 +- ld/testsuite/ld-s390/tlspic1_64.s | 4 +- ld/testsuite/ld-scripts/section-match-1.d | 2 +- sim/testsuite/d10v-elf/t-macros.i | 2 +- sim/testsuite/sim/bfin/divq.s | 2 +- sim/testsuite/sim/bfin/se_illegalcombination.S | 2 +- sim/testsuite/sim/bfin/se_undefinedinstruction1.S | 2 +- sim/testsuite/sim/bfin/se_undefinedinstruction2.S | 4 +- sim/testsuite/sim/fr30/addsp.cgs | 6 +-- sim/testsuite/sim/fr30/bc.cgs | 64 +++++++++++------------ sim/testsuite/sim/fr30/beq.cgs | 64 +++++++++++------------ sim/testsuite/sim/fr30/bge.cgs | 64 +++++++++++------------ sim/testsuite/sim/fr30/bgt.cgs | 64 +++++++++++------------ sim/testsuite/sim/fr30/bhi.cgs | 64 +++++++++++------------ sim/testsuite/sim/fr30/ble.cgs | 64 +++++++++++------------ sim/testsuite/sim/fr30/bls.cgs | 64 +++++++++++------------ sim/testsuite/sim/fr30/blt.cgs | 64 +++++++++++------------ sim/testsuite/sim/fr30/bn.cgs | 64 +++++++++++------------ sim/testsuite/sim/fr30/bnc.cgs | 64 +++++++++++------------ sim/testsuite/sim/fr30/bne.cgs | 64 +++++++++++------------ sim/testsuite/sim/fr30/bno.cgs | 64 +++++++++++------------ sim/testsuite/sim/fr30/bnv.cgs | 64 +++++++++++------------ sim/testsuite/sim/fr30/bp.cgs | 64 +++++++++++------------ sim/testsuite/sim/fr30/bra.cgs | 64 +++++++++++------------ sim/testsuite/sim/fr30/bv.cgs | 64 +++++++++++------------ sim/testsuite/sim/fr30/copld.cgs | 4 +- sim/testsuite/sim/fr30/copop.cgs | 4 +- sim/testsuite/sim/fr30/copst.cgs | 4 +- sim/testsuite/sim/fr30/copsv.cgs | 4 +- sim/testsuite/sim/fr30/enter.cgs | 4 +- sim/testsuite/sim/fr30/extsb.cgs | 8 +-- sim/testsuite/sim/fr30/extsh.cgs | 12 ++--- sim/testsuite/sim/fr30/extub.cgs | 10 ++-- sim/testsuite/sim/fr30/extuh.cgs | 14 ++--- sim/testsuite/sim/fr30/ldres.cgs | 4 +- sim/testsuite/sim/fr30/leave.cgs | 2 +- sim/testsuite/sim/fr30/nop.cgs | 2 +- sim/testsuite/sim/fr30/stres.cgs | 4 +- sim/testsuite/sim/fr30/xchb.cgs | 2 +- sim/testsuite/sim/h8300/ldc.s | 4 +- sim/testsuite/sim/h8300/stc.s | 4 +- sim/testsuite/sim/mips/hilo-hazard-3.s | 2 +- sim/testsuite/sim/mips/hilo-hazard-4.s | 2 +- sim/testsuite/sim/sh/fipr.s | 2 +- zlib/contrib/inflate86/inffast.S | 2 +- 62 files changed, 593 insertions(+), 593 deletions(-) diff --git a/gas/testsuite/gas/arm/local_function.d b/gas/testsuite/gas/arm/local_function.d index 2532f73..6d227d5 100644 --- a/gas/testsuite/gas/arm/local_function.d +++ b/gas/testsuite/gas/arm/local_function.d @@ -1,5 +1,5 @@ #objdump: -r -#name: Relocations agains local function symbols +#name: Relocations against local function symbols # This test is only valid on ELF based ports. #not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* *-*-vxworks diff --git a/gas/testsuite/gas/arm/req.s b/gas/testsuite/gas/arm/req.s index 1330e75..4399aee 100644 --- a/gas/testsuite/gas/arm/req.s +++ b/gas/testsuite/gas/arm/req.s @@ -37,5 +37,5 @@ test_dot_req_and_unreq: add FOO, FOO, FOO # Check that a second attempt to alias foo, using a mixed case - # verison of the name, will fail. + # version of the name, will fail. Foo .req r2 diff --git a/gas/testsuite/gas/arm/vfp1.s b/gas/testsuite/gas/arm/vfp1.s index 1a80877..ff8a5fb 100644 --- a/gas/testsuite/gas/arm/vfp1.s +++ b/gas/testsuite/gas/arm/vfp1.s @@ -3,7 +3,7 @@ .global F F: @ First we test the basic syntax and bit patterns of the opcodes. - @ Most of these tests deliberatly use d0/r0 to avoid setting + @ Most of these tests deliberately use d0/r0 to avoid setting @ any more bits than necessary. @ Comparison operations diff --git a/gas/testsuite/gas/arm/vfp1_t2.s b/gas/testsuite/gas/arm/vfp1_t2.s index dd596cb..763a34d 100644 --- a/gas/testsuite/gas/arm/vfp1_t2.s +++ b/gas/testsuite/gas/arm/vfp1_t2.s @@ -6,7 +6,7 @@ .global F F: @ First we test the basic syntax and bit patterns of the opcodes. - @ Most of these tests deliberatly use d0/r0 to avoid setting + @ Most of these tests deliberately use d0/r0 to avoid setting @ any more bits than necessary. @ Comparison operations diff --git a/gas/testsuite/gas/arm/vfp1xD.s b/gas/testsuite/gas/arm/vfp1xD.s index 0e603e9..a760c9b 100644 --- a/gas/testsuite/gas/arm/vfp1xD.s +++ b/gas/testsuite/gas/arm/vfp1xD.s @@ -3,7 +3,7 @@ .global F F: @ First we test the basic syntax and bit patterns of the opcodes. - @ Most of these tests deliberatly use s0/r0 to avoid setting + @ Most of these tests deliberately use s0/r0 to avoid setting @ any more bits than necessary. @ Comparison operations diff --git a/gas/testsuite/gas/arm/vfp1xD_t2.s b/gas/testsuite/gas/arm/vfp1xD_t2.s index 8e962c0..8372762 100644 --- a/gas/testsuite/gas/arm/vfp1xD_t2.s +++ b/gas/testsuite/gas/arm/vfp1xD_t2.s @@ -6,7 +6,7 @@ .global F F: @ First we test the basic syntax and bit patterns of the opcodes. - @ Most of these tests deliberatly use s0/r0 to avoid setting + @ Most of these tests deliberately use s0/r0 to avoid setting @ any more bits than necessary. @ Comparison operations diff --git a/gas/testsuite/gas/mcore/allinsn.s b/gas/testsuite/gas/mcore/allinsn.s index e9196e7..7f21e51 100644 --- a/gas/testsuite/gas/mcore/allinsn.s +++ b/gas/testsuite/gas/mcore/allinsn.s @@ -13,14 +13,14 @@ footext: test addc "r1,r2" // A double forward slash starts a line comment test addi "r3, 1" # So does a hash test addu "r4, r5" // White space between operands should be ignored - test and "r6,r7" ; test andi "r8,2" // A semicolon seperates statements + test and "r6,r7" ; test andi "r8,2" // A semicolon separates statements test andn "r9, r10" test asr "r11, R12" // Uppercase R is allowed as a register prefix test asrc "r13" test asri "r14,0x1f" test bclri "r15,0" test bf footext - test bgeni "sp, 7" // r0 can also be refered to as 'sp' + test bgeni "sp, 7" // r0 can also be referred to as 'sp' test BGENI "r0, 8" // Officially upper case or mixed case test BGENi "r0, 31" // mnemonics should not be allowed, but we relax this... test bgenr "r1, r2" diff --git a/gas/testsuite/gas/mips/24k-triple-stores-5.s b/gas/testsuite/gas/mips/24k-triple-stores-5.s index eb0e92e..a5823ee 100644 --- a/gas/testsuite/gas/mips/24k-triple-stores-5.s +++ b/gas/testsuite/gas/mips/24k-triple-stores-5.s @@ -1,4 +1,4 @@ -# Mix byte/half/word sizes with arbitary base register. +# Mix byte/half/word sizes with arbitrary base register. foo: # safe diff --git a/gas/testsuite/gas/mips/delay.d b/gas/testsuite/gas/mips/delay.d index 0c3ef08..63d7728 100644 --- a/gas/testsuite/gas/mips/delay.d +++ b/gas/testsuite/gas/mips/delay.d @@ -5,7 +5,7 @@ # # Gas should produce nop's after mtc1 and related # insn's if the target fpr is used in the -# immediatly following insn. See also nodelay.d. +# immediately following insn. See also nodelay.d. # .*: +file format .*mips.* diff --git a/gas/testsuite/gas/mips/nodelay.d b/gas/testsuite/gas/mips/nodelay.d index 10101f0..2b1ed5d 100644 --- a/gas/testsuite/gas/mips/nodelay.d +++ b/gas/testsuite/gas/mips/nodelay.d @@ -5,7 +5,7 @@ # For -mips4 # Gas should *not* produce nop's after mtc1 and related -# insn's if the target fpr is used in the immediatly +# insn's if the target fpr is used in the immediately # following insn. See also delay.d. # diff --git a/gas/testsuite/gas/mips/r5900-full.s b/gas/testsuite/gas/mips/r5900-full.s index 9560dc7..a5ca89d 100644 --- a/gas/testsuite/gas/mips/r5900-full.s +++ b/gas/testsuite/gas/mips/r5900-full.s @@ -48,7 +48,7 @@ stuff: # The cvt.w.s instruction of the R5900 does the same as trunc.w.s in MIPS I. # The cvt.w.s instruction of MIPS I doesn't exist in the R5900 CPU. - # For compatibilty the instruction trunc.w.s uses the opcode of cvt.w.s. + # For compatibility the instruction trunc.w.s uses the opcode of cvt.w.s. # cvt.w.s should not be used on R5900. trunc.w.s $f0, $f31 trunc.w.s $f31, $f0 diff --git a/gas/testsuite/gas/mips/r5900.s b/gas/testsuite/gas/mips/r5900.s index 022c4ab..3a16e28 100644 --- a/gas/testsuite/gas/mips/r5900.s +++ b/gas/testsuite/gas/mips/r5900.s @@ -44,7 +44,7 @@ stuff: # The cvt.w.s instruction of the R5900 does the same as trunc.w.s in MIPS I. # The cvt.w.s instruction of MIPS I doesn't exist in the R5900 CPU. - # For compatibilty the instruction trunc.w.s uses the opcode of cvt.w.s. + # For compatibility the instruction trunc.w.s uses the opcode of cvt.w.s. # cvt.w.s should not be used on R5900. trunc.w.s $f0, $f31 trunc.w.s $f31, $f0 diff --git a/gdb/testsuite/gdb.dwarf2/fission-reread.S b/gdb/testsuite/gdb.dwarf2/fission-reread.S index dc5885f..b00adb2 100644 --- a/gdb/testsuite/gdb.dwarf2/fission-reread.S +++ b/gdb/testsuite/gdb.dwarf2/fission-reread.S @@ -97,7 +97,7 @@ SYMBOL(main): .byte 0x87 .4byte .Lskeleton_debug_line0 /* DW_AT_stmt_list */ - /* Manually inserted to have a DW_AT_specification refering to + /* Manually inserted to have a DW_AT_specification referring to something and appearing ahead of it. */ .uleb128 0x8 /* DW_TAG_class_type */ .4byte .Ltu_class_type - .Ltu_start_dwo diff --git a/gdb/testsuite/gdb.dwarf2/pr13961.S b/gdb/testsuite/gdb.dwarf2/pr13961.S index afec8f8..1859a26 100644 --- a/gdb/testsuite/gdb.dwarf2/pr13961.S +++ b/gdb/testsuite/gdb.dwarf2/pr13961.S @@ -101,7 +101,7 @@ SYMBOL(main): .byte 0x87 .4byte .Ldebug_line0 /* DW_AT_stmt_list */ - /* Manually inserted to have a DW_AT_specification refering to + /* Manually inserted to have a DW_AT_specification referring to something and appearing ahead of it. */ .uleb128 0x8 /* DW_TAG_class_type */ .4byte .Ltu_class_type - .Ldebug_types0 @@ -178,7 +178,7 @@ SYMBOL(main): .byte 0x3 /* DW_OP_addr */ .4byte baz - /* Manually inserted to have a DW_AT_specification refering to + /* Manually inserted to have a DW_AT_specification referring to something and appearing ahead of it. */ .uleb128 0x8 /* DW_TAG_class_type */ .4byte .Lcu_class_type - .Ldebug_info0 /* DW_AT_specification */ diff --git a/ld/testsuite/ld-arm/stm32l4xx-fix-all.s b/ld/testsuite/ld-arm/stm32l4xx-fix-all.s index 580e5b2..e1e4a06 100644 --- a/ld/testsuite/ld-arm/stm32l4xx-fix-all.s +++ b/ld/testsuite/ld-arm/stm32l4xx-fix-all.s @@ -7,7 +7,7 @@ .thumb_func .global _start _start: - @ All LDM treatments for word acces <= 8 go through the same + @ All LDM treatments for word access <= 8 go through the same @ replication code, but decoding may vary ldm.w r9, {r1-r8} ldm.w r9!, {r1-r8} @@ -15,7 +15,7 @@ _start: ldmdb.w r9!, {r1-r8} pop {r1-r8} - @ All VLDM treatments for word acces <= 8 go through the same + @ All VLDM treatments for word access <= 8 go through the same @ replication code, but decoding may vary vldm r9, {s1-s8} vldm r6!, {s9-s16} diff --git a/ld/testsuite/ld-arm/thumb2-b-interwork.s b/ld/testsuite/ld-arm/thumb2-b-interwork.s index 4452a8f..2f82c47 100644 --- a/ld/testsuite/ld-arm/thumb2-b-interwork.s +++ b/ld/testsuite/ld-arm/thumb2-b-interwork.s @@ -1,4 +1,4 @@ -@ Test to ensure that a Thumb-2 B.W can branch to an ARM funtion. +@ Test to ensure that a Thumb-2 B.W can branch to an ARM function. .arch armv7-a .global _start diff --git a/ld/testsuite/ld-arm/thumb2-bl.s b/ld/testsuite/ld-arm/thumb2-bl.s index 80af810..306aa4e 100644 --- a/ld/testsuite/ld-arm/thumb2-bl.s +++ b/ld/testsuite/ld-arm/thumb2-bl.s @@ -1,5 +1,5 @@ @ Test to ensure that a Thumb-2 BL works with an offset that is -@ not permissable for Thumb-1. +@ not permissible for Thumb-1. .global _start .syntax unified diff --git a/ld/testsuite/ld-s390/tlspic1.s b/ld/testsuite/ld-s390/tlspic1.s index 28b9c3a..e423985 100644 --- a/ld/testsuite/ld-s390/tlspic1.s +++ b/ld/testsuite/ld-s390/tlspic1.s @@ -32,7 +32,7 @@ sh8: .long 264 .type fn1,@function .balign 64 fn1: - /* Funtion prolog */ + /* Function prolog */ stm %r6,%r14,24(%r15) bras %r13,.LTN1 /* Literal pool */ @@ -84,7 +84,7 @@ fn1: .LC22: .long sH2@gotntpoff .LTN1: - /* Funtion prolog */ + /* Function prolog */ lr %r14,%r15 l %r12,.LC0-.LT1(%r13) ahi %r15,-96 diff --git a/ld/testsuite/ld-s390/tlspic1_64.s b/ld/testsuite/ld-s390/tlspic1_64.s index 4e50008..31abd78 100644 --- a/ld/testsuite/ld-s390/tlspic1_64.s +++ b/ld/testsuite/ld-s390/tlspic1_64.s @@ -32,7 +32,7 @@ sh8: .long 264 .type fn1,@function .balign 64 fn1: - /* Funtion prolog */ + /* Function prolog */ stmg %r6,%r14,48(%r15) bras %r13,.LTN1 /* Literal pool */ @@ -80,7 +80,7 @@ fn1: .LC22: .quad sH2@gotntpoff .LTN1: - /* Funtion prolog */ + /* Function prolog */ lgr %r14,%r15 larl %r12,_GLOBAL_OFFSET_TABLE_ aghi %r15,-160 diff --git a/ld/testsuite/ld-scripts/section-match-1.d b/ld/testsuite/ld-scripts/section-match-1.d index c68dbb8..519f7cd 100644 --- a/ld/testsuite/ld-scripts/section-match-1.d +++ b/ld/testsuite/ld-scripts/section-match-1.d @@ -2,7 +2,7 @@ #ld: -T section-match-1.t #objdump: -s #notarget: *-*-osf* *-*-aix* *-*-pe *-*-*aout *-*-*oldld *-*-ecoff *-*-netbsd *-*-vms h8300-*-* tic30-*-* -# This test uses arbitary section names, which are not support by some +# This test uses arbitrary section names, which are not support by some # file formts. Also these section names must be present in the # output, not translated into some other name, eg .text diff --git a/sim/testsuite/d10v-elf/t-macros.i b/sim/testsuite/d10v-elf/t-macros.i index f424acf..0de38d4 100644 --- a/sim/testsuite/d10v-elf/t-macros.i +++ b/sim/testsuite/d10v-elf/t-macros.i @@ -170,7 +170,7 @@ _start: .data 1: ldi r1, 2f@word jmp r1 -;;; Successfull trap jumps back to here +;;; Successful trap jumps back to here .text ;;; Verify the PSW 2: mvfc r2, cr0 diff --git a/sim/testsuite/sim/bfin/divq.s b/sim/testsuite/sim/bfin/divq.s index 6cb881b..61880c7 100644 --- a/sim/testsuite/sim/bfin/divq.s +++ b/sim/testsuite/sim/bfin/divq.s @@ -7,7 +7,7 @@ start /* - * Evaluate given a signed integer dividend and signed interger divisor + * Evaluate given a signed integer dividend and signed integer divisor * input is: * r0 = dividend, or numerator * r1 = divisor, or denominator diff --git a/sim/testsuite/sim/bfin/se_illegalcombination.S b/sim/testsuite/sim/bfin/se_illegalcombination.S index 0fe5f27..bd8f333 100644 --- a/sim/testsuite/sim/bfin/se_illegalcombination.S +++ b/sim/testsuite/sim/bfin/se_illegalcombination.S @@ -2,7 +2,7 @@ // Description: Multi-issue Illegal Combinations # mach: bfin # sim: --environment operating -# xfail: "missing a few checks; hardware doesnt seem to match PRM?" bfin-* +# xfail: "missing a few checks; hardware doesn't seem to match PRM?" bfin-* #include "test.h" .include "testutils.inc" diff --git a/sim/testsuite/sim/bfin/se_undefinedinstruction1.S b/sim/testsuite/sim/bfin/se_undefinedinstruction1.S index 5337a74..fa1ab72 100644 --- a/sim/testsuite/sim/bfin/se_undefinedinstruction1.S +++ b/sim/testsuite/sim/bfin/se_undefinedinstruction1.S @@ -200,7 +200,7 @@ BEGIN: .dw 0x21 ; .dw 0x22 ; .dw 0x26 ; - .dw 0x27 ; // XXX: hardware doesnt trigger illegal exception ? + .dw 0x27 ; // XXX: hardware doesn't trigger illegal exception ? .dw 0x28 ; .dw 0x29 ; .dw 0x2A ; diff --git a/sim/testsuite/sim/bfin/se_undefinedinstruction2.S b/sim/testsuite/sim/bfin/se_undefinedinstruction2.S index d21e375..9d68ccb 100644 --- a/sim/testsuite/sim/bfin/se_undefinedinstruction2.S +++ b/sim/testsuite/sim/bfin/se_undefinedinstruction2.S @@ -175,12 +175,12 @@ BEGIN: .dw 0x10E ; .dw 0x124 ; .ifndef BFIN_HW - // XXX: hardware doesnt trigger illegal exception ? + // XXX: hardware doesn't trigger illegal exception ? .dw 0x125 ; .endif .dw 0x164 ; .ifndef BFIN_HW - // XXX: hardware doesnt trigger illegal exception ? + // XXX: hardware doesn't trigger illegal exception ? .dw 0x165 ; .endif .dw 0x128 ; diff --git a/sim/testsuite/sim/fr30/addsp.cgs b/sim/testsuite/sim/fr30/addsp.cgs index da5bc36..d12eefd 100644 --- a/sim/testsuite/sim/fr30/addsp.cgs +++ b/sim/testsuite/sim/fr30/addsp.cgs @@ -11,18 +11,18 @@ addsp: ; Test addsp $s10 mvr_h_gr sp,r7 ; save stack pointer permanently mvr_h_gr sp,r8 ; Shadow updated sp - set_cc 0x0f ; Condition codes are irrelevent + set_cc 0x0f ; Condition codes are irrelevant addsp 508 test_cc 1 1 1 1 inci_h_gr 508,r8 testr_h_gr r8,sp - set_cc 0x0e ; Condition codes are irrelevent + set_cc 0x0e ; Condition codes are irrelevant addsp 0 test_cc 1 1 1 0 testr_h_gr r8,sp - set_cc 0x0d ; Condition codes are irrelevent + set_cc 0x0d ; Condition codes are irrelevant addsp -512 test_cc 1 1 0 1 inci_h_gr -512,r8 diff --git a/sim/testsuite/sim/fr30/bc.cgs b/sim/testsuite/sim/fr30/bc.cgs index 0502625..e2233a1 100644 --- a/sim/testsuite/sim/fr30/bc.cgs +++ b/sim/testsuite/sim/fr30/bc.cgs @@ -9,101 +9,101 @@ .global bc bc: ; Test bc $label9 - set_cc 0x0f ; condition codes are irrelevent + set_cc 0x0f ; condition codes are irrelevant take_branch bc - set_cc 0x0e ; condition codes are irrelevent + set_cc 0x0e ; condition codes are irrelevant no_branch bc - set_cc 0x0d ; condition codes are irrelevent + set_cc 0x0d ; condition codes are irrelevant take_branch bc - set_cc 0x0c ; condition codes are irrelevent + set_cc 0x0c ; condition codes are irrelevant no_branch bc - set_cc 0x0b ; condition codes are irrelevent + set_cc 0x0b ; condition codes are irrelevant take_branch bc - set_cc 0x0a ; condition codes are irrelevent + set_cc 0x0a ; condition codes are irrelevant no_branch bc - set_cc 0x09 ; condition codes are irrelevent + set_cc 0x09 ; condition codes are irrelevant take_branch bc - set_cc 0x08 ; condition codes are irrelevent + set_cc 0x08 ; condition codes are irrelevant no_branch bc - set_cc 0x07 ; condition codes are irrelevent + set_cc 0x07 ; condition codes are irrelevant take_branch bc - set_cc 0x06 ; condition codes are irrelevent + set_cc 0x06 ; condition codes are irrelevant no_branch bc - set_cc 0x05 ; condition codes are irrelevent + set_cc 0x05 ; condition codes are irrelevant take_branch bc - set_cc 0x04 ; condition codes are irrelevent + set_cc 0x04 ; condition codes are irrelevant no_branch bc - set_cc 0x03 ; condition codes are irrelevent + set_cc 0x03 ; condition codes are irrelevant take_branch bc - set_cc 0x02 ; condition codes are irrelevent + set_cc 0x02 ; condition codes are irrelevant no_branch bc - set_cc 0x01 ; condition codes are irrelevent + set_cc 0x01 ; condition codes are irrelevant take_branch bc - set_cc 0x00 ; condition codes are irrelevent + set_cc 0x00 ; condition codes are irrelevant no_branch bc ; Test bc:d label9 - set_cc 0x0f ; condition codes are irrelevent + set_cc 0x0f ; condition codes are irrelevant take_branch_d bc:d 0xf - set_cc 0x0e ; condition codes are irrelevent + set_cc 0x0e ; condition codes are irrelevant no_branch_d bc:d 0xe - set_cc 0x0d ; condition codes are irrelevent + set_cc 0x0d ; condition codes are irrelevant take_branch_d bc:d 0xd - set_cc 0x0c ; condition codes are irrelevent + set_cc 0x0c ; condition codes are irrelevant no_branch_d bc:d 0xc - set_cc 0x0b ; condition codes are irrelevent + set_cc 0x0b ; condition codes are irrelevant take_branch_d bc:d 0xb - set_cc 0x0a ; condition codes are irrelevent + set_cc 0x0a ; condition codes are irrelevant no_branch_d bc:d 0xa - set_cc 0x09 ; condition codes are irrelevent + set_cc 0x09 ; condition codes are irrelevant take_branch_d bc:d 0x9 - set_cc 0x08 ; condition codes are irrelevent + set_cc 0x08 ; condition codes are irrelevant no_branch_d bc:d 0x8 - set_cc 0x07 ; condition codes are irrelevent + set_cc 0x07 ; condition codes are irrelevant take_branch_d bc:d 0x7 - set_cc 0x06 ; condition codes are irrelevent + set_cc 0x06 ; condition codes are irrelevant no_branch_d bc:d 0x6 - set_cc 0x05 ; condition codes are irrelevent + set_cc 0x05 ; condition codes are irrelevant take_branch_d bc:d 0x5 - set_cc 0x04 ; condition codes are irrelevent + set_cc 0x04 ; condition codes are irrelevant no_branch_d bc:d 0x4 - set_cc 0x03 ; condition codes are irrelevent + set_cc 0x03 ; condition codes are irrelevant take_branch_d bc:d 0x3 - set_cc 0x02 ; condition codes are irrelevent + set_cc 0x02 ; condition codes are irrelevant no_branch_d bc:d 0x2 - set_cc 0x01 ; condition codes are irrelevent + set_cc 0x01 ; condition codes are irrelevant take_branch_d bc:d 0x1 - set_cc 0x00 ; condition codes are irrelevent + set_cc 0x00 ; condition codes are irrelevant no_branch_d bc:d 0x0 pass diff --git a/sim/testsuite/sim/fr30/beq.cgs b/sim/testsuite/sim/fr30/beq.cgs index edd797e..443ebbe 100644 --- a/sim/testsuite/sim/fr30/beq.cgs +++ b/sim/testsuite/sim/fr30/beq.cgs @@ -9,101 +9,101 @@ .global beq beq: ; Test beq $label9 - set_cc 0x0f ; condition codes are irrelevent + set_cc 0x0f ; condition codes are irrelevant take_branch beq - set_cc 0x0e ; condition codes are irrelevent + set_cc 0x0e ; condition codes are irrelevant take_branch beq - set_cc 0x0d ; condition codes are irrelevent + set_cc 0x0d ; condition codes are irrelevant take_branch beq - set_cc 0x0c ; condition codes are irrelevent + set_cc 0x0c ; condition codes are irrelevant take_branch beq - set_cc 0x0b ; condition codes are irrelevent + set_cc 0x0b ; condition codes are irrelevant no_branch beq - set_cc 0x0a ; condition codes are irrelevent + set_cc 0x0a ; condition codes are irrelevant no_branch beq - set_cc 0x09 ; condition codes are irrelevent + set_cc 0x09 ; condition codes are irrelevant no_branch beq - set_cc 0x08 ; condition codes are irrelevent + set_cc 0x08 ; condition codes are irrelevant no_branch beq - set_cc 0x07 ; condition codes are irrelevent + set_cc 0x07 ; condition codes are irrelevant take_branch beq - set_cc 0x06 ; condition codes are irrelevent + set_cc 0x06 ; condition codes are irrelevant take_branch beq - set_cc 0x05 ; condition codes are irrelevent + set_cc 0x05 ; condition codes are irrelevant take_branch beq - set_cc 0x04 ; condition codes are irrelevent + set_cc 0x04 ; condition codes are irrelevant take_branch beq - set_cc 0x03 ; condition codes are irrelevent + set_cc 0x03 ; condition codes are irrelevant no_branch beq - set_cc 0x02 ; condition codes are irrelevent + set_cc 0x02 ; condition codes are irrelevant no_branch beq - set_cc 0x01 ; condition codes are irrelevent + set_cc 0x01 ; condition codes are irrelevant no_branch beq - set_cc 0x00 ; condition codes are irrelevent + set_cc 0x00 ; condition codes are irrelevant no_branch beq ; Test beq:d label9 - set_cc 0x0f ; condition codes are irrelevent + set_cc 0x0f ; condition codes are irrelevant take_branch_d beq:d 0xf - set_cc 0x0e ; condition codes are irrelevent + set_cc 0x0e ; condition codes are irrelevant take_branch_d beq:d 0xe - set_cc 0x0d ; condition codes are irrelevent + set_cc 0x0d ; condition codes are irrelevant take_branch_d beq:d 0xd - set_cc 0x0c ; condition codes are irrelevent + set_cc 0x0c ; condition codes are irrelevant take_branch_d beq:d 0xc - set_cc 0x0b ; condition codes are irrelevent + set_cc 0x0b ; condition codes are irrelevant no_branch_d beq:d 0xb - set_cc 0x0a ; condition codes are irrelevent + set_cc 0x0a ; condition codes are irrelevant no_branch_d beq:d 0xa - set_cc 0x09 ; condition codes are irrelevent + set_cc 0x09 ; condition codes are irrelevant no_branch_d beq:d 0x9 - set_cc 0x08 ; condition codes are irrelevent + set_cc 0x08 ; condition codes are irrelevant no_branch_d beq:d 0x8 - set_cc 0x07 ; condition codes are irrelevent + set_cc 0x07 ; condition codes are irrelevant take_branch_d beq:d 0x7 - set_cc 0x06 ; condition codes are irrelevent + set_cc 0x06 ; condition codes are irrelevant take_branch_d beq:d 0x6 - set_cc 0x05 ; condition codes are irrelevent + set_cc 0x05 ; condition codes are irrelevant take_branch_d beq:d 0x5 - set_cc 0x04 ; condition codes are irrelevent + set_cc 0x04 ; condition codes are irrelevant take_branch_d beq:d 0x4 - set_cc 0x03 ; condition codes are irrelevent + set_cc 0x03 ; condition codes are irrelevant no_branch_d beq:d 0x3 - set_cc 0x02 ; condition codes are irrelevent + set_cc 0x02 ; condition codes are irrelevant no_branch_d beq:d 0x2 - set_cc 0x01 ; condition codes are irrelevent + set_cc 0x01 ; condition codes are irrelevant no_branch_d beq:d 0x1 - set_cc 0x00 ; condition codes are irrelevent + set_cc 0x00 ; condition codes are irrelevant no_branch_d beq:d 0x0 pass diff --git a/sim/testsuite/sim/fr30/bge.cgs b/sim/testsuite/sim/fr30/bge.cgs index dd7796c..6db3f3e 100644 --- a/sim/testsuite/sim/fr30/bge.cgs +++ b/sim/testsuite/sim/fr30/bge.cgs @@ -9,101 +9,101 @@ .global bge bge: ; Test bge $label9 - set_cc 0x0f ; condition codes are irrelevent + set_cc 0x0f ; condition codes are irrelevant take_branch bge - set_cc 0x0e ; condition codes are irrelevent + set_cc 0x0e ; condition codes are irrelevant take_branch bge - set_cc 0x0d ; condition codes are irrelevent + set_cc 0x0d ; condition codes are irrelevant no_branch bge - set_cc 0x0c ; condition codes are irrelevent + set_cc 0x0c ; condition codes are irrelevant no_branch bge - set_cc 0x0b ; condition codes are irrelevent + set_cc 0x0b ; condition codes are irrelevant take_branch bge - set_cc 0x0a ; condition codes are irrelevent + set_cc 0x0a ; condition codes are irrelevant take_branch bge - set_cc 0x09 ; condition codes are irrelevent + set_cc 0x09 ; condition codes are irrelevant no_branch bge - set_cc 0x08 ; condition codes are irrelevent + set_cc 0x08 ; condition codes are irrelevant no_branch bge - set_cc 0x07 ; condition codes are irrelevent + set_cc 0x07 ; condition codes are irrelevant no_branch bge - set_cc 0x06 ; condition codes are irrelevent + set_cc 0x06 ; condition codes are irrelevant no_branch bge - set_cc 0x05 ; condition codes are irrelevent + set_cc 0x05 ; condition codes are irrelevant take_branch bge - set_cc 0x04 ; condition codes are irrelevent + set_cc 0x04 ; condition codes are irrelevant take_branch bge - set_cc 0x03 ; condition codes are irrelevent + set_cc 0x03 ; condition codes are irrelevant no_branch bge - set_cc 0x02 ; condition codes are irrelevent + set_cc 0x02 ; condition codes are irrelevant no_branch bge - set_cc 0x01 ; condition codes are irrelevent + set_cc 0x01 ; condition codes are irrelevant take_branch bge - set_cc 0x00 ; condition codes are irrelevent + set_cc 0x00 ; condition codes are irrelevant take_branch bge ; Test bge:d label9 - set_cc 0x0f ; condition codes are irrelevent + set_cc 0x0f ; condition codes are irrelevant take_branch_d bge:d 0xf - set_cc 0x0e ; condition codes are irrelevent + set_cc 0x0e ; condition codes are irrelevant take_branch_d bge:d 0xe - set_cc 0x0d ; condition codes are irrelevent + set_cc 0x0d ; condition codes are irrelevant no_branch_d bge:d 0xd - set_cc 0x0c ; condition codes are irrelevent + set_cc 0x0c ; condition codes are irrelevant no_branch_d bge:d 0xc - set_cc 0x0b ; condition codes are irrelevent + set_cc 0x0b ; condition codes are irrelevant take_branch_d bge:d 0xb - set_cc 0x0a ; condition codes are irrelevent + set_cc 0x0a ; condition codes are irrelevant take_branch_d bge:d 0xa - set_cc 0x09 ; condition codes are irrelevent + set_cc 0x09 ; condition codes are irrelevant no_branch_d bge:d 0x9 - set_cc 0x08 ; condition codes are irrelevent + set_cc 0x08 ; condition codes are irrelevant no_branch_d bge:d 0x8 - set_cc 0x07 ; condition codes are irrelevent + set_cc 0x07 ; condition codes are irrelevant no_branch_d bge:d 0x7 - set_cc 0x06 ; condition codes are irrelevent + set_cc 0x06 ; condition codes are irrelevant no_branch_d bge:d 0x6 - set_cc 0x05 ; condition codes are irrelevent + set_cc 0x05 ; condition codes are irrelevant take_branch_d bge:d 0x5 - set_cc 0x04 ; condition codes are irrelevent + set_cc 0x04 ; condition codes are irrelevant take_branch_d bge:d 0x4 - set_cc 0x03 ; condition codes are irrelevent + set_cc 0x03 ; condition codes are irrelevant no_branch_d bge:d 0x3 - set_cc 0x02 ; condition codes are irrelevent + set_cc 0x02 ; condition codes are irrelevant no_branch_d bge:d 0x2 - set_cc 0x01 ; condition codes are irrelevent + set_cc 0x01 ; condition codes are irrelevant take_branch_d bge:d 0x1 - set_cc 0x00 ; condition codes are irrelevent + set_cc 0x00 ; condition codes are irrelevant take_branch_d bge:d 0x0 pass diff --git a/sim/testsuite/sim/fr30/bgt.cgs b/sim/testsuite/sim/fr30/bgt.cgs index 525ac2e..f4924eb 100644 --- a/sim/testsuite/sim/fr30/bgt.cgs +++ b/sim/testsuite/sim/fr30/bgt.cgs @@ -9,101 +9,101 @@ .global bgt bgt: ; Test bgt $label9 - set_cc 0x0f ; condition codes are irrelevent + set_cc 0x0f ; condition codes are irrelevant no_branch bgt - set_cc 0x0e ; condition codes are irrelevent + set_cc 0x0e ; condition codes are irrelevant no_branch bgt - set_cc 0x0d ; condition codes are irrelevent + set_cc 0x0d ; condition codes are irrelevant no_branch bgt - set_cc 0x0c ; condition codes are irrelevent + set_cc 0x0c ; condition codes are irrelevant no_branch bgt - set_cc 0x0b ; condition codes are irrelevent + set_cc 0x0b ; condition codes are irrelevant take_branch bgt - set_cc 0x0a ; condition codes are irrelevent + set_cc 0x0a ; condition codes are irrelevant take_branch bgt - set_cc 0x09 ; condition codes are irrelevent + set_cc 0x09 ; condition codes are irrelevant no_branch bgt - set_cc 0x08 ; condition codes are irrelevent + set_cc 0x08 ; condition codes are irrelevant no_branch bgt - set_cc 0x07 ; condition codes are irrelevent + set_cc 0x07 ; condition codes are irrelevant no_branch bgt - set_cc 0x06 ; condition codes are irrelevent + set_cc 0x06 ; condition codes are irrelevant no_branch bgt - set_cc 0x05 ; condition codes are irrelevent + set_cc 0x05 ; condition codes are irrelevant no_branch bgt - set_cc 0x04 ; condition codes are irrelevent + set_cc 0x04 ; condition codes are irrelevant no_branch bgt - set_cc 0x03 ; condition codes are irrelevent + set_cc 0x03 ; condition codes are irrelevant no_branch bgt - set_cc 0x02 ; condition codes are irrelevent + set_cc 0x02 ; condition codes are irrelevant no_branch bgt - set_cc 0x01 ; condition codes are irrelevent + set_cc 0x01 ; condition codes are irrelevant take_branch bgt - set_cc 0x00 ; condition codes are irrelevent + set_cc 0x00 ; condition codes are irrelevant take_branch bgt ; Test bgt:d label9 - set_cc 0x0f ; condition codes are irrelevent + set_cc 0x0f ; condition codes are irrelevant no_branch_d bgt:d 0xf - set_cc 0x0e ; condition codes are irrelevent + set_cc 0x0e ; condition codes are irrelevant no_branch_d bgt:d 0xe - set_cc 0x0d ; condition codes are irrelevent + set_cc 0x0d ; condition codes are irrelevant no_branch_d bgt:d 0xd - set_cc 0x0c ; condition codes are irrelevent + set_cc 0x0c ; condition codes are irrelevant no_branch_d bgt:d 0xc - set_cc 0x0b ; condition codes are irrelevent + set_cc 0x0b ; condition codes are irrelevant take_branch_d bgt:d 0xb - set_cc 0x0a ; condition codes are irrelevent + set_cc 0x0a ; condition codes are irrelevant take_branch_d bgt:d 0xa - set_cc 0x09 ; condition codes are irrelevent + set_cc 0x09 ; condition codes are irrelevant no_branch_d bgt:d 0x9 - set_cc 0x08 ; condition codes are irrelevent + set_cc 0x08 ; condition codes are irrelevant no_branch_d bgt:d 0x8 - set_cc 0x07 ; condition codes are irrelevent + set_cc 0x07 ; condition codes are irrelevant no_branch_d bgt:d 0x7 - set_cc 0x06 ; condition codes are irrelevent + set_cc 0x06 ; condition codes are irrelevant no_branch_d bgt:d 0x6 - set_cc 0x05 ; condition codes are irrelevent + set_cc 0x05 ; condition codes are irrelevant no_branch_d bgt:d 0x5 - set_cc 0x04 ; condition codes are irrelevent + set_cc 0x04 ; condition codes are irrelevant no_branch_d bgt:d 0x4 - set_cc 0x03 ; condition codes are irrelevent + set_cc 0x03 ; condition codes are irrelevant no_branch_d bgt:d 0x3 - set_cc 0x02 ; condition codes are irrelevent + set_cc 0x02 ; condition codes are irrelevant no_branch_d bgt:d 0x2 - set_cc 0x01 ; condition codes are irrelevent + set_cc 0x01 ; condition codes are irrelevant take_branch_d bgt:d 0x1 - set_cc 0x00 ; condition codes are irrelevent + set_cc 0x00 ; condition codes are irrelevant take_branch_d bgt:d 0x0 pass diff --git a/sim/testsuite/sim/fr30/bhi.cgs b/sim/testsuite/sim/fr30/bhi.cgs index f5a1549..fb2bebf 100644 --- a/sim/testsuite/sim/fr30/bhi.cgs +++ b/sim/testsuite/sim/fr30/bhi.cgs @@ -9,101 +9,101 @@ .global bhi bhi: ; Test bhi $label9 - set_cc 0x0f ; condition codes are irrelevent + set_cc 0x0f ; condition codes are irrelevant no_branch bhi - set_cc 0x0e ; condition codes are irrelevent + set_cc 0x0e ; condition codes are irrelevant no_branch bhi - set_cc 0x0d ; condition codes are irrelevent + set_cc 0x0d ; condition codes are irrelevant no_branch bhi - set_cc 0x0c ; condition codes are irrelevent + set_cc 0x0c ; condition codes are irrelevant no_branch bhi - set_cc 0x0b ; condition codes are irrelevent + set_cc 0x0b ; condition codes are irrelevant no_branch bhi - set_cc 0x0a ; condition codes are irrelevent + set_cc 0x0a ; condition codes are irrelevant take_branch bhi - set_cc 0x09 ; condition codes are irrelevent + set_cc 0x09 ; condition codes are irrelevant no_branch bhi - set_cc 0x08 ; condition codes are irrelevent + set_cc 0x08 ; condition codes are irrelevant take_branch bhi - set_cc 0x07 ; condition codes are irrelevent + set_cc 0x07 ; condition codes are irrelevant no_branch bhi - set_cc 0x06 ; condition codes are irrelevent + set_cc 0x06 ; condition codes are irrelevant no_branch bhi - set_cc 0x05 ; condition codes are irrelevent + set_cc 0x05 ; condition codes are irrelevant no_branch bhi - set_cc 0x04 ; condition codes are irrelevent + set_cc 0x04 ; condition codes are irrelevant no_branch bhi - set_cc 0x03 ; condition codes are irrelevent + set_cc 0x03 ; condition codes are irrelevant no_branch bhi - set_cc 0x02 ; condition codes are irrelevent + set_cc 0x02 ; condition codes are irrelevant take_branch bhi - set_cc 0x01 ; condition codes are irrelevent + set_cc 0x01 ; condition codes are irrelevant no_branch bhi - set_cc 0x00 ; condition codes are irrelevent + set_cc 0x00 ; condition codes are irrelevant take_branch bhi ; Test bhi:d label9 - set_cc 0x0f ; condition codes are irrelevent + set_cc 0x0f ; condition codes are irrelevant no_branch_d bhi:d 0xf - set_cc 0x0e ; condition codes are irrelevent + set_cc 0x0e ; condition codes are irrelevant no_branch_d bhi:d 0xe - set_cc 0x0d ; condition codes are irrelevent + set_cc 0x0d ; condition codes are irrelevant no_branch_d bhi:d 0xd - set_cc 0x0c ; condition codes are irrelevent + set_cc 0x0c ; condition codes are irrelevant no_branch_d bhi:d 0xc - set_cc 0x0b ; condition codes are irrelevent + set_cc 0x0b ; condition codes are irrelevant no_branch_d bhi:d 0xb - set_cc 0x0a ; condition codes are irrelevent + set_cc 0x0a ; condition codes are irrelevant take_branch_d bhi:d 0xa - set_cc 0x09 ; condition codes are irrelevent + set_cc 0x09 ; condition codes are irrelevant no_branch_d bhi:d 0x9 - set_cc 0x08 ; condition codes are irrelevent + set_cc 0x08 ; condition codes are irrelevant take_branch_d bhi:d 0x8 - set_cc 0x07 ; condition codes are irrelevent + set_cc 0x07 ; condition codes are irrelevant no_branch_d bhi:d 0x7 - set_cc 0x06 ; condition codes are irrelevent + set_cc 0x06 ; condition codes are irrelevant no_branch_d bhi:d 0x6 - set_cc 0x05 ; condition codes are irrelevent + set_cc 0x05 ; condition codes are irrelevant no_branch_d bhi:d 0x5 - set_cc 0x04 ; condition codes are irrelevent + set_cc 0x04 ; condition codes are irrelevant no_branch_d bhi:d 0x4 - set_cc 0x03 ; condition codes are irrelevent + set_cc 0x03 ; condition codes are irrelevant no_branch_d bhi:d 0x3 - set_cc 0x02 ; condition codes are irrelevent + set_cc 0x02 ; condition codes are irrelevant take_branch_d bhi:d 0x2 - set_cc 0x01 ; condition codes are irrelevent + set_cc 0x01 ; condition codes are irrelevant no_branch_d bhi:d 0x1 - set_cc 0x00 ; condition codes are irrelevent + set_cc 0x00 ; condition codes are irrelevant take_branch_d bhi:d 0x0 pass diff --git a/sim/testsuite/sim/fr30/ble.cgs b/sim/testsuite/sim/fr30/ble.cgs index 1a33f78..ae361bb 100644 --- a/sim/testsuite/sim/fr30/ble.cgs +++ b/sim/testsuite/sim/fr30/ble.cgs @@ -9,101 +9,101 @@ .global ble ble: ; Test ble $label9 - set_cc 0x0f ; condition codes are irrelevent + set_cc 0x0f ; condition codes are irrelevant take_branch ble - set_cc 0x0e ; condition codes are irrelevent + set_cc 0x0e ; condition codes are irrelevant take_branch ble - set_cc 0x0d ; condition codes are irrelevent + set_cc 0x0d ; condition codes are irrelevant take_branch ble - set_cc 0x0c ; condition codes are irrelevent + set_cc 0x0c ; condition codes are irrelevant take_branch ble - set_cc 0x0b ; condition codes are irrelevent + set_cc 0x0b ; condition codes are irrelevant no_branch ble - set_cc 0x0a ; condition codes are irrelevent + set_cc 0x0a ; condition codes are irrelevant no_branch ble - set_cc 0x09 ; condition codes are irrelevent + set_cc 0x09 ; condition codes are irrelevant take_branch ble - set_cc 0x08 ; condition codes are irrelevent + set_cc 0x08 ; condition codes are irrelevant take_branch ble - set_cc 0x07 ; condition codes are irrelevent + set_cc 0x07 ; condition codes are irrelevant take_branch ble - set_cc 0x06 ; condition codes are irrelevent + set_cc 0x06 ; condition codes are irrelevant take_branch ble - set_cc 0x05 ; condition codes are irrelevent + set_cc 0x05 ; condition codes are irrelevant take_branch ble - set_cc 0x04 ; condition codes are irrelevent + set_cc 0x04 ; condition codes are irrelevant take_branch ble - set_cc 0x03 ; condition codes are irrelevent + set_cc 0x03 ; condition codes are irrelevant take_branch ble - set_cc 0x02 ; condition codes are irrelevent + set_cc 0x02 ; condition codes are irrelevant take_branch ble - set_cc 0x01 ; condition codes are irrelevent + set_cc 0x01 ; condition codes are irrelevant no_branch ble - set_cc 0x00 ; condition codes are irrelevent + set_cc 0x00 ; condition codes are irrelevant no_branch ble ; Test ble:d label9 - set_cc 0x0f ; condition codes are irrelevent + set_cc 0x0f ; condition codes are irrelevant take_branch_d ble:d 0xf - set_cc 0x0e ; condition codes are irrelevent + set_cc 0x0e ; condition codes are irrelevant take_branch_d ble:d 0xe - set_cc 0x0d ; condition codes are irrelevent + set_cc 0x0d ; condition codes are irrelevant take_branch_d ble:d 0xd - set_cc 0x0c ; condition codes are irrelevent + set_cc 0x0c ; condition codes are irrelevant take_branch_d ble:d 0xc - set_cc 0x0b ; condition codes are irrelevent + set_cc 0x0b ; condition codes are irrelevant no_branch_d ble:d 0xb - set_cc 0x0a ; condition codes are irrelevent + set_cc 0x0a ; condition codes are irrelevant no_branch_d ble:d 0xa - set_cc 0x09 ; condition codes are irrelevent + set_cc 0x09 ; condition codes are irrelevant take_branch_d ble:d 0x9 - set_cc 0x08 ; condition codes are irrelevent + set_cc 0x08 ; condition codes are irrelevant take_branch_d ble:d 0x8 - set_cc 0x07 ; condition codes are irrelevent + set_cc 0x07 ; condition codes are irrelevant take_branch_d ble:d 0x7 - set_cc 0x06 ; condition codes are irrelevent + set_cc 0x06 ; condition codes are irrelevant take_branch_d ble:d 0x6 - set_cc 0x05 ; condition codes are irrelevent + set_cc 0x05 ; condition codes are irrelevant take_branch_d ble:d 0x5 - set_cc 0x04 ; condition codes are irrelevent + set_cc 0x04 ; condition codes are irrelevant take_branch_d ble:d 0x4 - set_cc 0x03 ; condition codes are irrelevent + set_cc 0x03 ; condition codes are irrelevant take_branch_d ble:d 0x3 - set_cc 0x02 ; condition codes are irrelevent + set_cc 0x02 ; condition codes are irrelevant take_branch_d ble:d 0x2 - set_cc 0x01 ; condition codes are irrelevent + set_cc 0x01 ; condition codes are irrelevant no_branch_d ble:d 0x1 - set_cc 0x00 ; condition codes are irrelevent + set_cc 0x00 ; condition codes are irrelevant no_branch_d ble:d 0x0 pass diff --git a/sim/testsuite/sim/fr30/bls.cgs b/sim/testsuite/sim/fr30/bls.cgs index c0148b7..bd13fd5 100644 --- a/sim/testsuite/sim/fr30/bls.cgs +++ b/sim/testsuite/sim/fr30/bls.cgs @@ -9,101 +9,101 @@ .global bls bls: ; Test bls $label9 - set_cc 0x0f ; condition codes are irrelevent + set_cc 0x0f ; condition codes are irrelevant take_branch bls - set_cc 0x0e ; condition codes are irrelevent + set_cc 0x0e ; condition codes are irrelevant take_branch bls - set_cc 0x0d ; condition codes are irrelevent + set_cc 0x0d ; condition codes are irrelevant take_branch bls - set_cc 0x0c ; condition codes are irrelevent + set_cc 0x0c ; condition codes are irrelevant take_branch bls - set_cc 0x0b ; condition codes are irrelevent + set_cc 0x0b ; condition codes are irrelevant take_branch bls - set_cc 0x0a ; condition codes are irrelevent + set_cc 0x0a ; condition codes are irrelevant no_branch bls - set_cc 0x09 ; condition codes are irrelevent + set_cc 0x09 ; condition codes are irrelevant take_branch bls - set_cc 0x08 ; condition codes are irrelevent + set_cc 0x08 ; condition codes are irrelevant no_branch bls - set_cc 0x07 ; condition codes are irrelevent + set_cc 0x07 ; condition codes are irrelevant take_branch bls - set_cc 0x06 ; condition codes are irrelevent + set_cc 0x06 ; condition codes are irrelevant take_branch bls - set_cc 0x05 ; condition codes are irrelevent + set_cc 0x05 ; condition codes are irrelevant take_branch bls - set_cc 0x04 ; condition codes are irrelevent + set_cc 0x04 ; condition codes are irrelevant take_branch bls - set_cc 0x03 ; condition codes are irrelevent + set_cc 0x03 ; condition codes are irrelevant take_branch bls - set_cc 0x02 ; condition codes are irrelevent + set_cc 0x02 ; condition codes are irrelevant no_branch bls - set_cc 0x01 ; condition codes are irrelevent + set_cc 0x01 ; condition codes are irrelevant take_branch bls - set_cc 0x00 ; condition codes are irrelevent + set_cc 0x00 ; condition codes are irrelevant no_branch bls ; Test bls:d label9 - set_cc 0x0f ; condition codes are irrelevent + set_cc 0x0f ; condition codes are irrelevant take_branch_d bls:d 0xf - set_cc 0x0e ; condition codes are irrelevent + set_cc 0x0e ; condition codes are irrelevant take_branch_d bls:d 0xe - set_cc 0x0d ; condition codes are irrelevent + set_cc 0x0d ; condition codes are irrelevant take_branch_d bls:d 0xd - set_cc 0x0c ; condition codes are irrelevent + set_cc 0x0c ; condition codes are irrelevant take_branch_d bls:d 0xc - set_cc 0x0b ; condition codes are irrelevent + set_cc 0x0b ; condition codes are irrelevant take_branch_d bls:d 0xb - set_cc 0x0a ; condition codes are irrelevent + set_cc 0x0a ; condition codes are irrelevant no_branch_d bls:d 0xa - set_cc 0x09 ; condition codes are irrelevent + set_cc 0x09 ; condition codes are irrelevant take_branch_d bls:d 0x9 - set_cc 0x08 ; condition codes are irrelevent + set_cc 0x08 ; condition codes are irrelevant no_branch_d bls:d 0x8 - set_cc 0x07 ; condition codes are irrelevent + set_cc 0x07 ; condition codes are irrelevant take_branch_d bls:d 0x7 - set_cc 0x06 ; condition codes are irrelevent + set_cc 0x06 ; condition codes are irrelevant take_branch_d bls:d 0x6 - set_cc 0x05 ; condition codes are irrelevent + set_cc 0x05 ; condition codes are irrelevant take_branch_d bls:d 0x5 - set_cc 0x04 ; condition codes are irrelevent + set_cc 0x04 ; condition codes are irrelevant take_branch_d bls:d 0x4 - set_cc 0x03 ; condition codes are irrelevent + set_cc 0x03 ; condition codes are irrelevant take_branch_d bls:d 0x3 - set_cc 0x02 ; condition codes are irrelevent + set_cc 0x02 ; condition codes are irrelevant no_branch_d bls:d 0x2 - set_cc 0x01 ; condition codes are irrelevent + set_cc 0x01 ; condition codes are irrelevant take_branch_d bls:d 0x1 - set_cc 0x00 ; condition codes are irrelevent + set_cc 0x00 ; condition codes are irrelevant no_branch_d bls:d 0x0 pass diff --git a/sim/testsuite/sim/fr30/blt.cgs b/sim/testsuite/sim/fr30/blt.cgs index f7b6ff1..3b1222b 100644 --- a/sim/testsuite/sim/fr30/blt.cgs +++ b/sim/testsuite/sim/fr30/blt.cgs @@ -9,101 +9,101 @@ .global blt blt: ; Test blt $label9 - set_cc 0x0f ; condition codes are irrelevent + set_cc 0x0f ; condition codes are irrelevant no_branch blt - set_cc 0x0e ; condition codes are irrelevent + set_cc 0x0e ; condition codes are irrelevant no_branch blt - set_cc 0x0d ; condition codes are irrelevent + set_cc 0x0d ; condition codes are irrelevant take_branch blt - set_cc 0x0c ; condition codes are irrelevent + set_cc 0x0c ; condition codes are irrelevant take_branch blt - set_cc 0x0b ; condition codes are irrelevent + set_cc 0x0b ; condition codes are irrelevant no_branch blt - set_cc 0x0a ; condition codes are irrelevent + set_cc 0x0a ; condition codes are irrelevant no_branch blt - set_cc 0x09 ; condition codes are irrelevent + set_cc 0x09 ; condition codes are irrelevant take_branch blt - set_cc 0x08 ; condition codes are irrelevent + set_cc 0x08 ; condition codes are irrelevant take_branch blt - set_cc 0x07 ; condition codes are irrelevent + set_cc 0x07 ; condition codes are irrelevant take_branch blt - set_cc 0x06 ; condition codes are irrelevent + set_cc 0x06 ; condition codes are irrelevant take_branch blt - set_cc 0x05 ; condition codes are irrelevent + set_cc 0x05 ; condition codes are irrelevant no_branch blt - set_cc 0x04 ; condition codes are irrelevent + set_cc 0x04 ; condition codes are irrelevant no_branch blt - set_cc 0x03 ; condition codes are irrelevent + set_cc 0x03 ; condition codes are irrelevant take_branch blt - set_cc 0x02 ; condition codes are irrelevent + set_cc 0x02 ; condition codes are irrelevant take_branch blt - set_cc 0x01 ; condition codes are irrelevent + set_cc 0x01 ; condition codes are irrelevant no_branch blt - set_cc 0x00 ; condition codes are irrelevent + set_cc 0x00 ; condition codes are irrelevant no_branch blt ; Test blt:d label9 - set_cc 0x0f ; condition codes are irrelevent + set_cc 0x0f ; condition codes are irrelevant no_branch_d blt:d 0xf - set_cc 0x0e ; condition codes are irrelevent + set_cc 0x0e ; condition codes are irrelevant no_branch_d blt:d 0xe - set_cc 0x0d ; condition codes are irrelevent + set_cc 0x0d ; condition codes are irrelevant take_branch_d blt:d 0xd - set_cc 0x0c ; condition codes are irrelevent + set_cc 0x0c ; condition codes are irrelevant take_branch_d blt:d 0xc - set_cc 0x0b ; condition codes are irrelevent + set_cc 0x0b ; condition codes are irrelevant no_branch_d blt:d 0xb - set_cc 0x0a ; condition codes are irrelevent + set_cc 0x0a ; condition codes are irrelevant no_branch_d blt:d 0xa - set_cc 0x09 ; condition codes are irrelevent + set_cc 0x09 ; condition codes are irrelevant take_branch_d blt:d 0x9 - set_cc 0x08 ; condition codes are irrelevent + set_cc 0x08 ; condition codes are irrelevant take_branch_d blt:d 0x8 - set_cc 0x07 ; condition codes are irrelevent + set_cc 0x07 ; condition codes are irrelevant take_branch_d blt:d 0x7 - set_cc 0x06 ; condition codes are irrelevent + set_cc 0x06 ; condition codes are irrelevant take_branch_d blt:d 0x6 - set_cc 0x05 ; condition codes are irrelevent + set_cc 0x05 ; condition codes are irrelevant no_branch_d blt:d 0x5 - set_cc 0x04 ; condition codes are irrelevent + set_cc 0x04 ; condition codes are irrelevant no_branch_d blt:d 0x4 - set_cc 0x03 ; condition codes are irrelevent + set_cc 0x03 ; condition codes are irrelevant take_branch_d blt:d 0x3 - set_cc 0x02 ; condition codes are irrelevent + set_cc 0x02 ; condition codes are irrelevant take_branch_d blt:d 0x2 - set_cc 0x01 ; condition codes are irrelevent + set_cc 0x01 ; condition codes are irrelevant no_branch_d blt:d 0x1 - set_cc 0x00 ; condition codes are irrelevent + set_cc 0x00 ; condition codes are irrelevant no_branch_d blt:d 0x0 pass diff --git a/sim/testsuite/sim/fr30/bn.cgs b/sim/testsuite/sim/fr30/bn.cgs index 45858fc..10e57ad 100644 --- a/sim/testsuite/sim/fr30/bn.cgs +++ b/sim/testsuite/sim/fr30/bn.cgs @@ -9,101 +9,101 @@ .global bn bn: ; Test bn $label9 - set_cc 0x0f ; condition codes are irrelevent + set_cc 0x0f ; condition codes are irrelevant take_branch bn - set_cc 0x0e ; condition codes are irrelevent + set_cc 0x0e ; condition codes are irrelevant take_branch bn - set_cc 0x0d ; condition codes are irrelevent + set_cc 0x0d ; condition codes are irrelevant take_branch bn - set_cc 0x0c ; condition codes are irrelevent + set_cc 0x0c ; condition codes are irrelevant take_branch bn - set_cc 0x0b ; condition codes are irrelevent + set_cc 0x0b ; condition codes are irrelevant take_branch bn - set_cc 0x0a ; condition codes are irrelevent + set_cc 0x0a ; condition codes are irrelevant take_branch bn - set_cc 0x09 ; condition codes are irrelevent + set_cc 0x09 ; condition codes are irrelevant take_branch bn - set_cc 0x08 ; condition codes are irrelevent + set_cc 0x08 ; condition codes are irrelevant take_branch bn - set_cc 0x07 ; condition codes are irrelevent + set_cc 0x07 ; condition codes are irrelevant no_branch bn - set_cc 0x06 ; condition codes are irrelevent + set_cc 0x06 ; condition codes are irrelevant no_branch bn - set_cc 0x05 ; condition codes are irrelevent + set_cc 0x05 ; condition codes are irrelevant no_branch bn - set_cc 0x04 ; condition codes are irrelevent + set_cc 0x04 ; condition codes are irrelevant no_branch bn - set_cc 0x03 ; condition codes are irrelevent + set_cc 0x03 ; condition codes are irrelevant no_branch bn - set_cc 0x02 ; condition codes are irrelevent + set_cc 0x02 ; condition codes are irrelevant no_branch bn - set_cc 0x01 ; condition codes are irrelevent + set_cc 0x01 ; condition codes are irrelevant no_branch bn - set_cc 0x00 ; condition codes are irrelevent + set_cc 0x00 ; condition codes are irrelevant no_branch bn ; Test bn:d label9 - set_cc 0x0f ; condition codes are irrelevent + set_cc 0x0f ; condition codes are irrelevant take_branch_d bn:d 0xf - set_cc 0x0e ; condition codes are irrelevent + set_cc 0x0e ; condition codes are irrelevant take_branch_d bn:d 0xe - set_cc 0x0d ; condition codes are irrelevent + set_cc 0x0d ; condition codes are irrelevant take_branch_d bn:d 0xd - set_cc 0x0c ; condition codes are irrelevent + set_cc 0x0c ; condition codes are irrelevant take_branch_d bn:d 0xc - set_cc 0x0b ; condition codes are irrelevent + set_cc 0x0b ; condition codes are irrelevant take_branch_d bn:d 0xb - set_cc 0x0a ; condition codes are irrelevent + set_cc 0x0a ; condition codes are irrelevant take_branch_d bn:d 0xa - set_cc 0x09 ; condition codes are irrelevent + set_cc 0x09 ; condition codes are irrelevant take_branch_d bn:d 0x9 - set_cc 0x08 ; condition codes are irrelevent + set_cc 0x08 ; condition codes are irrelevant take_branch_d bn:d 0x8 - set_cc 0x07 ; condition codes are irrelevent + set_cc 0x07 ; condition codes are irrelevant no_branch_d bn:d 0x7 - set_cc 0x06 ; condition codes are irrelevent + set_cc 0x06 ; condition codes are irrelevant no_branch_d bn:d 0x6 - set_cc 0x05 ; condition codes are irrelevent + set_cc 0x05 ; condition codes are irrelevant no_branch_d bn:d 0x5 - set_cc 0x04 ; condition codes are irrelevent + set_cc 0x04 ; condition codes are irrelevant no_branch_d bn:d 0x4 - set_cc 0x03 ; condition codes are irrelevent + set_cc 0x03 ; condition codes are irrelevant no_branch_d bn:d 0x3 - set_cc 0x02 ; condition codes are irrelevent + set_cc 0x02 ; condition codes are irrelevant no_branch_d bn:d 0x2 - set_cc 0x01 ; condition codes are irrelevent + set_cc 0x01 ; condition codes are irrelevant no_branch_d bn:d 0x1 - set_cc 0x00 ; condition codes are irrelevent + set_cc 0x00 ; condition codes are irrelevant no_branch_d bn:d 0x0 pass diff --git a/sim/testsuite/sim/fr30/bnc.cgs b/sim/testsuite/sim/fr30/bnc.cgs index 9968c43..5d86cee 100644 --- a/sim/testsuite/sim/fr30/bnc.cgs +++ b/sim/testsuite/sim/fr30/bnc.cgs @@ -9,101 +9,101 @@ .global bnc bc: ; Test bnc $label9 - set_cc 0x0f ; condition codes are irrelevent + set_cc 0x0f ; condition codes are irrelevant no_branch bnc - set_cc 0x0e ; condition codes are irrelevent + set_cc 0x0e ; condition codes are irrelevant take_branch bnc - set_cc 0x0d ; condition codes are irrelevent + set_cc 0x0d ; condition codes are irrelevant no_branch bnc - set_cc 0x0c ; condition codes are irrelevent + set_cc 0x0c ; condition codes are irrelevant take_branch bnc - set_cc 0x0b ; condition codes are irrelevent + set_cc 0x0b ; condition codes are irrelevant no_branch bnc - set_cc 0x0a ; condition codes are irrelevent + set_cc 0x0a ; condition codes are irrelevant take_branch bnc - set_cc 0x09 ; condition codes are irrelevent + set_cc 0x09 ; condition codes are irrelevant no_branch bnc - set_cc 0x08 ; condition codes are irrelevent + set_cc 0x08 ; condition codes are irrelevant take_branch bnc - set_cc 0x07 ; condition codes are irrelevent + set_cc 0x07 ; condition codes are irrelevant no_branch bnc - set_cc 0x06 ; condition codes are irrelevent + set_cc 0x06 ; condition codes are irrelevant take_branch bnc - set_cc 0x05 ; condition codes are irrelevent + set_cc 0x05 ; condition codes are irrelevant no_branch bnc - set_cc 0x04 ; condition codes are irrelevent + set_cc 0x04 ; condition codes are irrelevant take_branch bnc - set_cc 0x03 ; condition codes are irrelevent + set_cc 0x03 ; condition codes are irrelevant no_branch bnc - set_cc 0x02 ; condition codes are irrelevent + set_cc 0x02 ; condition codes are irrelevant take_branch bnc - set_cc 0x01 ; condition codes are irrelevent + set_cc 0x01 ; condition codes are irrelevant no_branch bnc - set_cc 0x00 ; condition codes are irrelevent + set_cc 0x00 ; condition codes are irrelevant take_branch bnc ; Test bnc:d label9 - set_cc 0x0f ; condition codes are irrelevent + set_cc 0x0f ; condition codes are irrelevant no_branch_d bnc:d 0xf - set_cc 0x0e ; condition codes are irrelevent + set_cc 0x0e ; condition codes are irrelevant take_branch_d bnc:d 0xe - set_cc 0x0d ; condition codes are irrelevent + set_cc 0x0d ; condition codes are irrelevant no_branch_d bnc:d 0xd - set_cc 0x0c ; condition codes are irrelevent + set_cc 0x0c ; condition codes are irrelevant take_branch_d bnc:d 0xc - set_cc 0x0b ; condition codes are irrelevent + set_cc 0x0b ; condition codes are irrelevant no_branch_d bnc:d 0xb - set_cc 0x0a ; condition codes are irrelevent + set_cc 0x0a ; condition codes are irrelevant take_branch_d bnc:d 0xa - set_cc 0x09 ; condition codes are irrelevent + set_cc 0x09 ; condition codes are irrelevant no_branch_d bnc:d 0x9 - set_cc 0x08 ; condition codes are irrelevent + set_cc 0x08 ; condition codes are irrelevant take_branch_d bnc:d 0x8 - set_cc 0x07 ; condition codes are irrelevent + set_cc 0x07 ; condition codes are irrelevant no_branch_d bnc:d 0x7 - set_cc 0x06 ; condition codes are irrelevent + set_cc 0x06 ; condition codes are irrelevant take_branch_d bnc:d 0x6 - set_cc 0x05 ; condition codes are irrelevent + set_cc 0x05 ; condition codes are irrelevant no_branch_d bnc:d 0x5 - set_cc 0x04 ; condition codes are irrelevent + set_cc 0x04 ; condition codes are irrelevant take_branch_d bnc:d 0x4 - set_cc 0x03 ; condition codes are irrelevent + set_cc 0x03 ; condition codes are irrelevant no_branch_d bnc:d 0x3 - set_cc 0x02 ; condition codes are irrelevent + set_cc 0x02 ; condition codes are irrelevant take_branch_d bnc:d 0x2 - set_cc 0x01 ; condition codes are irrelevent + set_cc 0x01 ; condition codes are irrelevant no_branch_d bnc:d 0x1 - set_cc 0x00 ; condition codes are irrelevent + set_cc 0x00 ; condition codes are irrelevant take_branch_d bnc:d 0x0 pass diff --git a/sim/testsuite/sim/fr30/bne.cgs b/sim/testsuite/sim/fr30/bne.cgs index 58971de..6ada810 100644 --- a/sim/testsuite/sim/fr30/bne.cgs +++ b/sim/testsuite/sim/fr30/bne.cgs @@ -9,101 +9,101 @@ .global bne bne: ; Test bne $label9 - set_cc 0x0f ; condition codes are irrelevent + set_cc 0x0f ; condition codes are irrelevant no_branch bne - set_cc 0x0e ; condition codes are irrelevent + set_cc 0x0e ; condition codes are irrelevant no_branch bne - set_cc 0x0d ; condition codes are irrelevent + set_cc 0x0d ; condition codes are irrelevant no_branch bne - set_cc 0x0c ; condition codes are irrelevent + set_cc 0x0c ; condition codes are irrelevant no_branch bne - set_cc 0x0b ; condition codes are irrelevent + set_cc 0x0b ; condition codes are irrelevant take_branch bne - set_cc 0x0a ; condition codes are irrelevent + set_cc 0x0a ; condition codes are irrelevant take_branch bne - set_cc 0x09 ; condition codes are irrelevent + set_cc 0x09 ; condition codes are irrelevant take_branch bne - set_cc 0x08 ; condition codes are irrelevent + set_cc 0x08 ; condition codes are irrelevant take_branch bne - set_cc 0x07 ; condition codes are irrelevent + set_cc 0x07 ; condition codes are irrelevant no_branch bne - set_cc 0x06 ; condition codes are irrelevent + set_cc 0x06 ; condition codes are irrelevant no_branch bne - set_cc 0x05 ; condition codes are irrelevent + set_cc 0x05 ; condition codes are irrelevant no_branch bne - set_cc 0x04 ; condition codes are irrelevent + set_cc 0x04 ; condition codes are irrelevant no_branch bne - set_cc 0x03 ; condition codes are irrelevent + set_cc 0x03 ; condition codes are irrelevant take_branch bne - set_cc 0x02 ; condition codes are irrelevent + set_cc 0x02 ; condition codes are irrelevant take_branch bne - set_cc 0x01 ; condition codes are irrelevent + set_cc 0x01 ; condition codes are irrelevant take_branch bne - set_cc 0x00 ; condition codes are irrelevent + set_cc 0x00 ; condition codes are irrelevant take_branch bne ; Test bne:d label9 - set_cc 0x0f ; condition codes are irrelevent + set_cc 0x0f ; condition codes are irrelevant no_branch_d bne:d 0xf - set_cc 0x0e ; condition codes are irrelevent + set_cc 0x0e ; condition codes are irrelevant no_branch_d bne:d 0xe - set_cc 0x0d ; condition codes are irrelevent + set_cc 0x0d ; condition codes are irrelevant no_branch_d bne:d 0xd - set_cc 0x0c ; condition codes are irrelevent + set_cc 0x0c ; condition codes are irrelevant no_branch_d bne:d 0xc - set_cc 0x0b ; condition codes are irrelevent + set_cc 0x0b ; condition codes are irrelevant take_branch_d bne:d 0xb - set_cc 0x0a ; condition codes are irrelevent + set_cc 0x0a ; condition codes are irrelevant take_branch_d bne:d 0xa - set_cc 0x09 ; condition codes are irrelevent + set_cc 0x09 ; condition codes are irrelevant take_branch_d bne:d 0x9 - set_cc 0x08 ; condition codes are irrelevent + set_cc 0x08 ; condition codes are irrelevant take_branch_d bne:d 0x8 - set_cc 0x07 ; condition codes are irrelevent + set_cc 0x07 ; condition codes are irrelevant no_branch_d bne:d 0x7 - set_cc 0x06 ; condition codes are irrelevent + set_cc 0x06 ; condition codes are irrelevant no_branch_d bne:d 0x6 - set_cc 0x05 ; condition codes are irrelevent + set_cc 0x05 ; condition codes are irrelevant no_branch_d bne:d 0x5 - set_cc 0x04 ; condition codes are irrelevent + set_cc 0x04 ; condition codes are irrelevant no_branch_d bne:d 0x4 - set_cc 0x03 ; condition codes are irrelevent + set_cc 0x03 ; condition codes are irrelevant take_branch_d bne:d 0x3 - set_cc 0x02 ; condition codes are irrelevent + set_cc 0x02 ; condition codes are irrelevant take_branch_d bne:d 0x2 - set_cc 0x01 ; condition codes are irrelevent + set_cc 0x01 ; condition codes are irrelevant take_branch_d bne:d 0x1 - set_cc 0x00 ; condition codes are irrelevent + set_cc 0x00 ; condition codes are irrelevant take_branch_d bne:d 0x0 pass diff --git a/sim/testsuite/sim/fr30/bno.cgs b/sim/testsuite/sim/fr30/bno.cgs index faef9ba..17f1356 100644 --- a/sim/testsuite/sim/fr30/bno.cgs +++ b/sim/testsuite/sim/fr30/bno.cgs @@ -9,101 +9,101 @@ .global bno bno: ; Test bno $label9 - set_cc 0x0f ; condition codes are irrelevent + set_cc 0x0f ; condition codes are irrelevant no_branch bno - set_cc 0x0e ; condition codes are irrelevent + set_cc 0x0e ; condition codes are irrelevant no_branch bno - set_cc 0x0d ; condition codes are irrelevent + set_cc 0x0d ; condition codes are irrelevant no_branch bno - set_cc 0x0c ; condition codes are irrelevent + set_cc 0x0c ; condition codes are irrelevant no_branch bno - set_cc 0x0b ; condition codes are irrelevent + set_cc 0x0b ; condition codes are irrelevant no_branch bno - set_cc 0x0a ; condition codes are irrelevent + set_cc 0x0a ; condition codes are irrelevant no_branch bno - set_cc 0x09 ; condition codes are irrelevent + set_cc 0x09 ; condition codes are irrelevant no_branch bno - set_cc 0x08 ; condition codes are irrelevent + set_cc 0x08 ; condition codes are irrelevant no_branch bno - set_cc 0x07 ; condition codes are irrelevent + set_cc 0x07 ; condition codes are irrelevant no_branch bno - set_cc 0x06 ; condition codes are irrelevent + set_cc 0x06 ; condition codes are irrelevant no_branch bno - set_cc 0x05 ; condition codes are irrelevent + set_cc 0x05 ; condition codes are irrelevant no_branch bno - set_cc 0x04 ; condition codes are irrelevent + set_cc 0x04 ; condition codes are irrelevant no_branch bno - set_cc 0x03 ; condition codes are irrelevent + set_cc 0x03 ; condition codes are irrelevant no_branch bno - set_cc 0x02 ; condition codes are irrelevent + set_cc 0x02 ; condition codes are irrelevant no_branch bno - set_cc 0x01 ; condition codes are irrelevent + set_cc 0x01 ; condition codes are irrelevant no_branch bno - set_cc 0x00 ; condition codes are irrelevent + set_cc 0x00 ; condition codes are irrelevant no_branch bno ; Test bno:d label9 - set_cc 0x0f ; condition codes are irrelevent + set_cc 0x0f ; condition codes are irrelevant no_branch_d bno:d 0xf - set_cc 0x0e ; condition codes are irrelevent + set_cc 0x0e ; condition codes are irrelevant no_branch_d bno:d 0xe - set_cc 0x0d ; condition codes are irrelevent + set_cc 0x0d ; condition codes are irrelevant no_branch_d bno:d 0xd - set_cc 0x0c ; condition codes are irrelevent + set_cc 0x0c ; condition codes are irrelevant no_branch_d bno:d 0xc - set_cc 0x0b ; condition codes are irrelevent + set_cc 0x0b ; condition codes are irrelevant no_branch_d bno:d 0xb - set_cc 0x0a ; condition codes are irrelevent + set_cc 0x0a ; condition codes are irrelevant no_branch_d bno:d 0xa - set_cc 0x09 ; condition codes are irrelevent + set_cc 0x09 ; condition codes are irrelevant no_branch_d bno:d 0x9 - set_cc 0x08 ; condition codes are irrelevent + set_cc 0x08 ; condition codes are irrelevant no_branch_d bno:d 0x8 - set_cc 0x07 ; condition codes are irrelevent + set_cc 0x07 ; condition codes are irrelevant no_branch_d bno:d 0x7 - set_cc 0x06 ; condition codes are irrelevent + set_cc 0x06 ; condition codes are irrelevant no_branch_d bno:d 0x6 - set_cc 0x05 ; condition codes are irrelevent + set_cc 0x05 ; condition codes are irrelevant no_branch_d bno:d 0x5 - set_cc 0x04 ; condition codes are irrelevent + set_cc 0x04 ; condition codes are irrelevant no_branch_d bno:d 0x4 - set_cc 0x03 ; condition codes are irrelevent + set_cc 0x03 ; condition codes are irrelevant no_branch_d bno:d 0x3 - set_cc 0x02 ; condition codes are irrelevent + set_cc 0x02 ; condition codes are irrelevant no_branch_d bno:d 0x2 - set_cc 0x01 ; condition codes are irrelevent + set_cc 0x01 ; condition codes are irrelevant no_branch_d bno:d 0x1 - set_cc 0x00 ; condition codes are irrelevent + set_cc 0x00 ; condition codes are irrelevant no_branch_d bno:d 0x0 pass diff --git a/sim/testsuite/sim/fr30/bnv.cgs b/sim/testsuite/sim/fr30/bnv.cgs index 7615abd..995dbb4 100644 --- a/sim/testsuite/sim/fr30/bnv.cgs +++ b/sim/testsuite/sim/fr30/bnv.cgs @@ -9,101 +9,101 @@ .global bnv bnv: ; Test bnv $label9 - set_cc 0x0f ; condition codes are irrelevent + set_cc 0x0f ; condition codes are irrelevant no_branch bnv - set_cc 0x0e ; condition codes are irrelevent + set_cc 0x0e ; condition codes are irrelevant no_branch bnv - set_cc 0x0d ; condition codes are irrelevent + set_cc 0x0d ; condition codes are irrelevant take_branch bnv - set_cc 0x0c ; condition codes are irrelevent + set_cc 0x0c ; condition codes are irrelevant take_branch bnv - set_cc 0x0b ; condition codes are irrelevent + set_cc 0x0b ; condition codes are irrelevant no_branch bnv - set_cc 0x0a ; condition codes are irrelevent + set_cc 0x0a ; condition codes are irrelevant no_branch bnv - set_cc 0x09 ; condition codes are irrelevent + set_cc 0x09 ; condition codes are irrelevant take_branch bnv - set_cc 0x08 ; condition codes are irrelevent + set_cc 0x08 ; condition codes are irrelevant take_branch bnv - set_cc 0x07 ; condition codes are irrelevent + set_cc 0x07 ; condition codes are irrelevant no_branch bnv - set_cc 0x06 ; condition codes are irrelevent + set_cc 0x06 ; condition codes are irrelevant no_branch bnv - set_cc 0x05 ; condition codes are irrelevent + set_cc 0x05 ; condition codes are irrelevant take_branch bnv - set_cc 0x04 ; condition codes are irrelevent + set_cc 0x04 ; condition codes are irrelevant take_branch bnv - set_cc 0x03 ; condition codes are irrelevent + set_cc 0x03 ; condition codes are irrelevant no_branch bnv - set_cc 0x02 ; condition codes are irrelevent + set_cc 0x02 ; condition codes are irrelevant no_branch bnv - set_cc 0x01 ; condition codes are irrelevent + set_cc 0x01 ; condition codes are irrelevant take_branch bnv - set_cc 0x00 ; condition codes are irrelevent + set_cc 0x00 ; condition codes are irrelevant take_branch bnv ; Test bnv:d label9 - set_cc 0x0f ; condition codes are irrelevent + set_cc 0x0f ; condition codes are irrelevant no_branch_d bnv:d 0xf - set_cc 0x0e ; condition codes are irrelevent + set_cc 0x0e ; condition codes are irrelevant no_branch_d bnv:d 0xe - set_cc 0x0d ; condition codes are irrelevent + set_cc 0x0d ; condition codes are irrelevant take_branch_d bnv:d 0xd - set_cc 0x0c ; condition codes are irrelevent + set_cc 0x0c ; condition codes are irrelevant take_branch_d bnv:d 0xc - set_cc 0x0b ; condition codes are irrelevent + set_cc 0x0b ; condition codes are irrelevant no_branch_d bnv:d 0xb - set_cc 0x0a ; condition codes are irrelevent + set_cc 0x0a ; condition codes are irrelevant no_branch_d bnv:d 0xa - set_cc 0x09 ; condition codes are irrelevent + set_cc 0x09 ; condition codes are irrelevant take_branch_d bnv:d 0x9 - set_cc 0x08 ; condition codes are irrelevent + set_cc 0x08 ; condition codes are irrelevant take_branch_d bnv:d 0x8 - set_cc 0x07 ; condition codes are irrelevent + set_cc 0x07 ; condition codes are irrelevant no_branch_d bnv:d 0x7 - set_cc 0x06 ; condition codes are irrelevent + set_cc 0x06 ; condition codes are irrelevant no_branch_d bnv:d 0x6 - set_cc 0x05 ; condition codes are irrelevent + set_cc 0x05 ; condition codes are irrelevant take_branch_d bnv:d 0x5 - set_cc 0x04 ; condition codes are irrelevent + set_cc 0x04 ; condition codes are irrelevant take_branch_d bnv:d 0x4 - set_cc 0x03 ; condition codes are irrelevent + set_cc 0x03 ; condition codes are irrelevant no_branch_d bnv:d 0x3 - set_cc 0x02 ; condition codes are irrelevent + set_cc 0x02 ; condition codes are irrelevant no_branch_d bnv:d 0x2 - set_cc 0x01 ; condition codes are irrelevent + set_cc 0x01 ; condition codes are irrelevant take_branch_d bnv:d 0x1 - set_cc 0x00 ; condition codes are irrelevent + set_cc 0x00 ; condition codes are irrelevant take_branch_d bnv:d 0x0 pass diff --git a/sim/testsuite/sim/fr30/bp.cgs b/sim/testsuite/sim/fr30/bp.cgs index 3753283..e89426a 100644 --- a/sim/testsuite/sim/fr30/bp.cgs +++ b/sim/testsuite/sim/fr30/bp.cgs @@ -9,101 +9,101 @@ .global bp bp: ; Test bp $label9 - set_cc 0x0f ; condition codes are irrelevent + set_cc 0x0f ; condition codes are irrelevant no_branch bp - set_cc 0x0e ; condition codes are irrelevent + set_cc 0x0e ; condition codes are irrelevant no_branch bp - set_cc 0x0d ; condition codes are irrelevent + set_cc 0x0d ; condition codes are irrelevant no_branch bp - set_cc 0x0c ; condition codes are irrelevent + set_cc 0x0c ; condition codes are irrelevant no_branch bp - set_cc 0x0b ; condition codes are irrelevent + set_cc 0x0b ; condition codes are irrelevant no_branch bp - set_cc 0x0a ; condition codes are irrelevent + set_cc 0x0a ; condition codes are irrelevant no_branch bp - set_cc 0x09 ; condition codes are irrelevent + set_cc 0x09 ; condition codes are irrelevant no_branch bp - set_cc 0x08 ; condition codes are irrelevent + set_cc 0x08 ; condition codes are irrelevant no_branch bp - set_cc 0x07 ; condition codes are irrelevent + set_cc 0x07 ; condition codes are irrelevant take_branch bp - set_cc 0x06 ; condition codes are irrelevent + set_cc 0x06 ; condition codes are irrelevant take_branch bp - set_cc 0x05 ; condition codes are irrelevent + set_cc 0x05 ; condition codes are irrelevant take_branch bp - set_cc 0x04 ; condition codes are irrelevent + set_cc 0x04 ; condition codes are irrelevant take_branch bp - set_cc 0x03 ; condition codes are irrelevent + set_cc 0x03 ; condition codes are irrelevant take_branch bp - set_cc 0x02 ; condition codes are irrelevent + set_cc 0x02 ; condition codes are irrelevant take_branch bp - set_cc 0x01 ; condition codes are irrelevent + set_cc 0x01 ; condition codes are irrelevant take_branch bp - set_cc 0x00 ; condition codes are irrelevent + set_cc 0x00 ; condition codes are irrelevant take_branch bp ; Test bp:d label9 - set_cc 0x0f ; condition codes are irrelevent + set_cc 0x0f ; condition codes are irrelevant no_branch_d bp:d 0xf - set_cc 0x0e ; condition codes are irrelevent + set_cc 0x0e ; condition codes are irrelevant no_branch_d bp:d 0xe - set_cc 0x0d ; condition codes are irrelevent + set_cc 0x0d ; condition codes are irrelevant no_branch_d bp:d 0xd - set_cc 0x0c ; condition codes are irrelevent + set_cc 0x0c ; condition codes are irrelevant no_branch_d bp:d 0xc - set_cc 0x0b ; condition codes are irrelevent + set_cc 0x0b ; condition codes are irrelevant no_branch_d bp:d 0xb - set_cc 0x0a ; condition codes are irrelevent + set_cc 0x0a ; condition codes are irrelevant no_branch_d bp:d 0xa - set_cc 0x09 ; condition codes are irrelevent + set_cc 0x09 ; condition codes are irrelevant no_branch_d bp:d 0x9 - set_cc 0x08 ; condition codes are irrelevent + set_cc 0x08 ; condition codes are irrelevant no_branch_d bp:d 0x8 - set_cc 0x07 ; condition codes are irrelevent + set_cc 0x07 ; condition codes are irrelevant take_branch_d bp:d 0x7 - set_cc 0x06 ; condition codes are irrelevent + set_cc 0x06 ; condition codes are irrelevant take_branch_d bp:d 0x6 - set_cc 0x05 ; condition codes are irrelevent + set_cc 0x05 ; condition codes are irrelevant take_branch_d bp:d 0x5 - set_cc 0x04 ; condition codes are irrelevent + set_cc 0x04 ; condition codes are irrelevant take_branch_d bp:d 0x4 - set_cc 0x03 ; condition codes are irrelevent + set_cc 0x03 ; condition codes are irrelevant take_branch_d bp:d 0x3 - set_cc 0x02 ; condition codes are irrelevent + set_cc 0x02 ; condition codes are irrelevant take_branch_d bp:d 0x2 - set_cc 0x01 ; condition codes are irrelevent + set_cc 0x01 ; condition codes are irrelevant take_branch_d bp:d 0x1 - set_cc 0x00 ; condition codes are irrelevent + set_cc 0x00 ; condition codes are irrelevant take_branch_d bp:d 0x0 pass diff --git a/sim/testsuite/sim/fr30/bra.cgs b/sim/testsuite/sim/fr30/bra.cgs index 3732f74..4afc585 100644 --- a/sim/testsuite/sim/fr30/bra.cgs +++ b/sim/testsuite/sim/fr30/bra.cgs @@ -9,101 +9,101 @@ .global bra bra: ; Test bra $label9 - set_cc 0x0f ; condition codes are irrelevent + set_cc 0x0f ; condition codes are irrelevant take_branch bra - set_cc 0x0e ; condition codes are irrelevent + set_cc 0x0e ; condition codes are irrelevant take_branch bra - set_cc 0x0d ; condition codes are irrelevent + set_cc 0x0d ; condition codes are irrelevant take_branch bra - set_cc 0x0c ; condition codes are irrelevent + set_cc 0x0c ; condition codes are irrelevant take_branch bra - set_cc 0x0b ; condition codes are irrelevent + set_cc 0x0b ; condition codes are irrelevant take_branch bra - set_cc 0x0a ; condition codes are irrelevent + set_cc 0x0a ; condition codes are irrelevant take_branch bra - set_cc 0x09 ; condition codes are irrelevent + set_cc 0x09 ; condition codes are irrelevant take_branch bra - set_cc 0x08 ; condition codes are irrelevent + set_cc 0x08 ; condition codes are irrelevant take_branch bra - set_cc 0x07 ; condition codes are irrelevent + set_cc 0x07 ; condition codes are irrelevant take_branch bra - set_cc 0x06 ; condition codes are irrelevent + set_cc 0x06 ; condition codes are irrelevant take_branch bra - set_cc 0x05 ; condition codes are irrelevent + set_cc 0x05 ; condition codes are irrelevant take_branch bra - set_cc 0x04 ; condition codes are irrelevent + set_cc 0x04 ; condition codes are irrelevant take_branch bra - set_cc 0x03 ; condition codes are irrelevent + set_cc 0x03 ; condition codes are irrelevant take_branch bra - set_cc 0x02 ; condition codes are irrelevent + set_cc 0x02 ; condition codes are irrelevant take_branch bra - set_cc 0x01 ; condition codes are irrelevent + set_cc 0x01 ; condition codes are irrelevant take_branch bra - set_cc 0x00 ; condition codes are irrelevent + set_cc 0x00 ; condition codes are irrelevant take_branch bra ; Test bra:d label9 - set_cc 0x0f ; condition codes are irrelevent + set_cc 0x0f ; condition codes are irrelevant take_branch_d bra:d 0xf - set_cc 0x0e ; condition codes are irrelevent + set_cc 0x0e ; condition codes are irrelevant take_branch_d bra:d 0xe - set_cc 0x0d ; condition codes are irrelevent + set_cc 0x0d ; condition codes are irrelevant take_branch_d bra:d 0xd - set_cc 0x0c ; condition codes are irrelevent + set_cc 0x0c ; condition codes are irrelevant take_branch_d bra:d 0xc - set_cc 0x0b ; condition codes are irrelevent + set_cc 0x0b ; condition codes are irrelevant take_branch_d bra:d 0xb - set_cc 0x0a ; condition codes are irrelevent + set_cc 0x0a ; condition codes are irrelevant take_branch_d bra:d 0xa - set_cc 0x09 ; condition codes are irrelevent + set_cc 0x09 ; condition codes are irrelevant take_branch_d bra:d 0x9 - set_cc 0x08 ; condition codes are irrelevent + set_cc 0x08 ; condition codes are irrelevant take_branch_d bra:d 0x8 - set_cc 0x07 ; condition codes are irrelevent + set_cc 0x07 ; condition codes are irrelevant take_branch_d bra:d 0x7 - set_cc 0x06 ; condition codes are irrelevent + set_cc 0x06 ; condition codes are irrelevant take_branch_d bra:d 0x6 - set_cc 0x05 ; condition codes are irrelevent + set_cc 0x05 ; condition codes are irrelevant take_branch_d bra:d 0x5 - set_cc 0x04 ; condition codes are irrelevent + set_cc 0x04 ; condition codes are irrelevant take_branch_d bra:d 0x4 - set_cc 0x03 ; condition codes are irrelevent + set_cc 0x03 ; condition codes are irrelevant take_branch_d bra:d 0x3 - set_cc 0x02 ; condition codes are irrelevent + set_cc 0x02 ; condition codes are irrelevant take_branch_d bra:d 0x2 - set_cc 0x01 ; condition codes are irrelevent + set_cc 0x01 ; condition codes are irrelevant take_branch_d bra:d 0x1 - set_cc 0x00 ; condition codes are irrelevent + set_cc 0x00 ; condition codes are irrelevant take_branch_d bra:d 0x0 pass diff --git a/sim/testsuite/sim/fr30/bv.cgs b/sim/testsuite/sim/fr30/bv.cgs index 68cb9acf..0a421e5 100644 --- a/sim/testsuite/sim/fr30/bv.cgs +++ b/sim/testsuite/sim/fr30/bv.cgs @@ -9,101 +9,101 @@ .global bv bv: ; Test bv $label9 - set_cc 0x0f ; condition codes are irrelevent + set_cc 0x0f ; condition codes are irrelevant take_branch bv - set_cc 0x0e ; condition codes are irrelevent + set_cc 0x0e ; condition codes are irrelevant take_branch bv - set_cc 0x0d ; condition codes are irrelevent + set_cc 0x0d ; condition codes are irrelevant no_branch bv - set_cc 0x0c ; condition codes are irrelevent + set_cc 0x0c ; condition codes are irrelevant no_branch bv - set_cc 0x0b ; condition codes are irrelevent + set_cc 0x0b ; condition codes are irrelevant take_branch bv - set_cc 0x0a ; condition codes are irrelevent + set_cc 0x0a ; condition codes are irrelevant take_branch bv - set_cc 0x09 ; condition codes are irrelevent + set_cc 0x09 ; condition codes are irrelevant no_branch bv - set_cc 0x08 ; condition codes are irrelevent + set_cc 0x08 ; condition codes are irrelevant no_branch bv - set_cc 0x07 ; condition codes are irrelevent + set_cc 0x07 ; condition codes are irrelevant take_branch bv - set_cc 0x06 ; condition codes are irrelevent + set_cc 0x06 ; condition codes are irrelevant take_branch bv - set_cc 0x05 ; condition codes are irrelevent + set_cc 0x05 ; condition codes are irrelevant no_branch bv - set_cc 0x04 ; condition codes are irrelevent + set_cc 0x04 ; condition codes are irrelevant no_branch bv - set_cc 0x03 ; condition codes are irrelevent + set_cc 0x03 ; condition codes are irrelevant take_branch bv - set_cc 0x02 ; condition codes are irrelevent + set_cc 0x02 ; condition codes are irrelevant take_branch bv - set_cc 0x01 ; condition codes are irrelevent + set_cc 0x01 ; condition codes are irrelevant no_branch bv - set_cc 0x00 ; condition codes are irrelevent + set_cc 0x00 ; condition codes are irrelevant no_branch bv ; Test bv:d label9 - set_cc 0x0f ; condition codes are irrelevent + set_cc 0x0f ; condition codes are irrelevant take_branch_d bv:d 0xf - set_cc 0x0e ; condition codes are irrelevent + set_cc 0x0e ; condition codes are irrelevant take_branch_d bv:d 0xe - set_cc 0x0d ; condition codes are irrelevent + set_cc 0x0d ; condition codes are irrelevant no_branch_d bv:d 0xd - set_cc 0x0c ; condition codes are irrelevent + set_cc 0x0c ; condition codes are irrelevant no_branch_d bv:d 0xc - set_cc 0x0b ; condition codes are irrelevent + set_cc 0x0b ; condition codes are irrelevant take_branch_d bv:d 0xb - set_cc 0x0a ; condition codes are irrelevent + set_cc 0x0a ; condition codes are irrelevant take_branch_d bv:d 0xa - set_cc 0x09 ; condition codes are irrelevent + set_cc 0x09 ; condition codes are irrelevant no_branch_d bv:d 0x9 - set_cc 0x08 ; condition codes are irrelevent + set_cc 0x08 ; condition codes are irrelevant no_branch_d bv:d 0x8 - set_cc 0x07 ; condition codes are irrelevent + set_cc 0x07 ; condition codes are irrelevant take_branch_d bv:d 0x7 - set_cc 0x06 ; condition codes are irrelevent + set_cc 0x06 ; condition codes are irrelevant take_branch_d bv:d 0x6 - set_cc 0x05 ; condition codes are irrelevent + set_cc 0x05 ; condition codes are irrelevant no_branch_d bv:d 0x5 - set_cc 0x04 ; condition codes are irrelevent + set_cc 0x04 ; condition codes are irrelevant no_branch_d bv:d 0x4 - set_cc 0x03 ; condition codes are irrelevent + set_cc 0x03 ; condition codes are irrelevant take_branch_d bv:d 0x3 - set_cc 0x02 ; condition codes are irrelevent + set_cc 0x02 ; condition codes are irrelevant take_branch_d bv:d 0x2 - set_cc 0x01 ; condition codes are irrelevent + set_cc 0x01 ; condition codes are irrelevant no_branch_d bv:d 0x1 - set_cc 0x00 ; condition codes are irrelevent + set_cc 0x00 ; condition codes are irrelevant no_branch_d bv:d 0x0 pass diff --git a/sim/testsuite/sim/fr30/copld.cgs b/sim/testsuite/sim/fr30/copld.cgs index e0ababb..2273243 100644 --- a/sim/testsuite/sim/fr30/copld.cgs +++ b/sim/testsuite/sim/fr30/copld.cgs @@ -10,11 +10,11 @@ copld: ; Test copld copld $u4,$cc,$Rj,CRi ; The current implementation is a noop - set_cc 0x0f ; Condition codes are irrelevent + set_cc 0x0f ; Condition codes are irrelevant copld 0,0,r0,cr15 test_cc 1 1 1 1 - set_cc 0x0e ; Condition codes are irrelevent + set_cc 0x0e ; Condition codes are irrelevant copld 15,255,r15,cr0 test_cc 1 1 1 0 diff --git a/sim/testsuite/sim/fr30/copop.cgs b/sim/testsuite/sim/fr30/copop.cgs index b0afd77..3fe785a 100644 --- a/sim/testsuite/sim/fr30/copop.cgs +++ b/sim/testsuite/sim/fr30/copop.cgs @@ -10,11 +10,11 @@ copop: ; Test copop copop $u4,$cc,$CRj,CRi ; The current implementation is a noop - set_cc 0x0f ; Condition codes are irrelevent + set_cc 0x0f ; Condition codes are irrelevant copop 0,0,cr0,cr15 test_cc 1 1 1 1 - set_cc 0x0e ; Condition codes are irrelevent + set_cc 0x0e ; Condition codes are irrelevant copop 15,255,cr0,cr15 test_cc 1 1 1 0 diff --git a/sim/testsuite/sim/fr30/copst.cgs b/sim/testsuite/sim/fr30/copst.cgs index 00120b2..034b920 100644 --- a/sim/testsuite/sim/fr30/copst.cgs +++ b/sim/testsuite/sim/fr30/copst.cgs @@ -10,11 +10,11 @@ copst: ; Test copst copst $u4,$cc,$CRj,Ri ; The current implementation is a noop - set_cc 0x0f ; Condition codes are irrelevent + set_cc 0x0f ; Condition codes are irrelevant copst 0,0,cr0,r15 test_cc 1 1 1 1 - set_cc 0x0e ; Condition codes are irrelevent + set_cc 0x0e ; Condition codes are irrelevant copst 15,255,cr15,r0 test_cc 1 1 1 0 diff --git a/sim/testsuite/sim/fr30/copsv.cgs b/sim/testsuite/sim/fr30/copsv.cgs index e00a4f5..45b3e98 100644 --- a/sim/testsuite/sim/fr30/copsv.cgs +++ b/sim/testsuite/sim/fr30/copsv.cgs @@ -10,11 +10,11 @@ copsv: ; Test copsv copsv $u4,$cc,$CRj,Ri ; The current implementation is a noop - set_cc 0x0f ; Condition codes are irrelevent + set_cc 0x0f ; Condition codes are irrelevant copsv 0,0,cr0,r15 test_cc 1 1 1 1 - set_cc 0x0e ; Condition codes are irrelevent + set_cc 0x0e ; Condition codes are irrelevant copsv 15,255,cr15,r0 test_cc 1 1 1 0 diff --git a/sim/testsuite/sim/fr30/enter.cgs b/sim/testsuite/sim/fr30/enter.cgs index ae75e16..7d20845 100644 --- a/sim/testsuite/sim/fr30/enter.cgs +++ b/sim/testsuite/sim/fr30/enter.cgs @@ -12,7 +12,7 @@ enter: mvr_h_gr sp,r7 ; save stack pointer mvr_h_gr sp,r8 ; shadow stack pointer mvr_h_gr sp,r14 ; Initialize - set_cc 0x0f ; Condition codes are irrelevent + set_cc 0x0f ; Condition codes are irrelevant enter 0 test_cc 1 1 1 1 testr_h_gr r8,sp @@ -22,7 +22,7 @@ enter: mvr_h_gr sp,r8 ; shadow stack pointer mvr_h_gr r14,r9 ; save - set_cc 0x0e ; Condition codes are irrelevent + set_cc 0x0e ; Condition codes are irrelevant enter 0x3fc test_cc 1 1 1 0 inci_h_gr -4,r8 diff --git a/sim/testsuite/sim/fr30/extsb.cgs b/sim/testsuite/sim/fr30/extsb.cgs index 6a18d7e..8d4158a 100644 --- a/sim/testsuite/sim/fr30/extsb.cgs +++ b/sim/testsuite/sim/fr30/extsb.cgs @@ -10,25 +10,25 @@ extsb: ; Test extsb $Ri mvi_h_gr 0,r7 - set_cc 0x0f ; Condition codes are irrelevent + set_cc 0x0f ; Condition codes are irrelevant extsb r7 test_cc 1 1 1 1 test_h_gr 0,r7 mvi_h_gr 0x7f,r7 - set_cc 0x0e ; Condition codes are irrelevent + set_cc 0x0e ; Condition codes are irrelevant extsb r7 test_cc 1 1 1 0 test_h_gr 0x7f,r7 mvi_h_gr 0x80,r7 - set_cc 0x0d ; Condition codes are irrelevent + set_cc 0x0d ; Condition codes are irrelevant extsb r7 test_cc 1 1 0 1 test_h_gr 0xffffff80,r7 mvi_h_gr 0xffffff7f,r7 - set_cc 0x0c ; Condition codes are irrelevent + set_cc 0x0c ; Condition codes are irrelevant extsb r7 test_cc 1 1 0 0 test_h_gr 0x7f,r7 diff --git a/sim/testsuite/sim/fr30/extsh.cgs b/sim/testsuite/sim/fr30/extsh.cgs index eb12fd0..1e575ee 100644 --- a/sim/testsuite/sim/fr30/extsh.cgs +++ b/sim/testsuite/sim/fr30/extsh.cgs @@ -10,37 +10,37 @@ extsh: ; Test extsh $Ri mvi_h_gr 0,r7 - set_cc 0x0f ; Condition codes are irrelevent + set_cc 0x0f ; Condition codes are irrelevant extsh r7 test_cc 1 1 1 1 test_h_gr 0,r7 mvi_h_gr 0x7f,r7 - set_cc 0x0e ; Condition codes are irrelevent + set_cc 0x0e ; Condition codes are irrelevant extsh r7 test_cc 1 1 1 0 test_h_gr 0x7f,r7 mvi_h_gr 0x80,r7 - set_cc 0x0d ; Condition codes are irrelevent + set_cc 0x0d ; Condition codes are irrelevant extsh r7 test_cc 1 1 0 1 test_h_gr 0x80,r7 mvi_h_gr 0x7fff,r7 - set_cc 0x0c ; Condition codes are irrelevent + set_cc 0x0c ; Condition codes are irrelevant extsh r7 test_cc 1 1 0 0 test_h_gr 0x7fff,r7 mvi_h_gr 0x8000,r7 - set_cc 0x0b ; Condition codes are irrelevent + set_cc 0x0b ; Condition codes are irrelevant extsh r7 test_cc 1 0 1 1 test_h_gr 0xffff8000,r7 mvi_h_gr 0xffff7fff,r7 - set_cc 0x0a ; Condition codes are irrelevent + set_cc 0x0a ; Condition codes are irrelevant extsh r7 test_cc 1 0 1 0 test_h_gr 0x7fff,r7 diff --git a/sim/testsuite/sim/fr30/extub.cgs b/sim/testsuite/sim/fr30/extub.cgs index ddcc683..846f95f 100644 --- a/sim/testsuite/sim/fr30/extub.cgs +++ b/sim/testsuite/sim/fr30/extub.cgs @@ -10,31 +10,31 @@ extub: ; Test extub $Ri mvi_h_gr 0,r7 - set_cc 0x0f ; Condition codes are irrelevent + set_cc 0x0f ; Condition codes are irrelevant extub r7 test_cc 1 1 1 1 test_h_gr 0,r7 mvi_h_gr 0x7f,r7 - set_cc 0x0e ; Condition codes are irrelevent + set_cc 0x0e ; Condition codes are irrelevant extub r7 test_cc 1 1 1 0 test_h_gr 0x7f,r7 mvi_h_gr 0x80,r7 - set_cc 0x0d ; Condition codes are irrelevent + set_cc 0x0d ; Condition codes are irrelevant extub r7 test_cc 1 1 0 1 test_h_gr 0x80,r7 mvi_h_gr 0xffffff7f,r7 - set_cc 0x0c ; Condition codes are irrelevent + set_cc 0x0c ; Condition codes are irrelevant extub r7 test_cc 1 1 0 0 test_h_gr 0x7f,r7 mvi_h_gr 0xffffff80,r7 - set_cc 0x0b ; Condition codes are irrelevent + set_cc 0x0b ; Condition codes are irrelevant extub r7 test_cc 1 0 1 1 test_h_gr 0x80,r7 diff --git a/sim/testsuite/sim/fr30/extuh.cgs b/sim/testsuite/sim/fr30/extuh.cgs index fa2579e..c4ed4ad 100644 --- a/sim/testsuite/sim/fr30/extuh.cgs +++ b/sim/testsuite/sim/fr30/extuh.cgs @@ -10,43 +10,43 @@ extuh: ; Test extuh $Ri mvi_h_gr 0,r7 - set_cc 0x0f ; Condition codes are irrelevent + set_cc 0x0f ; Condition codes are irrelevant extuh r7 test_cc 1 1 1 1 test_h_gr 0,r7 mvi_h_gr 0x7f,r7 - set_cc 0x0e ; Condition codes are irrelevent + set_cc 0x0e ; Condition codes are irrelevant extuh r7 test_cc 1 1 1 0 test_h_gr 0x7f,r7 mvi_h_gr 0x80,r7 - set_cc 0x0d ; Condition codes are irrelevent + set_cc 0x0d ; Condition codes are irrelevant extuh r7 test_cc 1 1 0 1 test_h_gr 0x80,r7 mvi_h_gr 0x7fff,r7 - set_cc 0x0e ; Condition codes are irrelevent + set_cc 0x0e ; Condition codes are irrelevant extuh r7 test_cc 1 1 1 0 test_h_gr 0x7fff,r7 mvi_h_gr 0x8000,r7 - set_cc 0x0d ; Condition codes are irrelevent + set_cc 0x0d ; Condition codes are irrelevant extuh r7 test_cc 1 1 0 1 test_h_gr 0x8000,r7 mvi_h_gr 0xffff7fff,r7 - set_cc 0x0c ; Condition codes are irrelevent + set_cc 0x0c ; Condition codes are irrelevant extuh r7 test_cc 1 1 0 0 test_h_gr 0x7fff,r7 mvi_h_gr 0xffff8000,r7 - set_cc 0x0b ; Condition codes are irrelevent + set_cc 0x0b ; Condition codes are irrelevant extuh r7 test_cc 1 0 1 1 test_h_gr 0x8000,r7 diff --git a/sim/testsuite/sim/fr30/ldres.cgs b/sim/testsuite/sim/fr30/ldres.cgs index 0083489..c03e341 100644 --- a/sim/testsuite/sim/fr30/ldres.cgs +++ b/sim/testsuite/sim/fr30/ldres.cgs @@ -11,13 +11,13 @@ ldres: ; Test ldres $@Ri+,$u4 ; The current implementation simply increments Ri mvi_h_gr 0x1000,r7 - set_cc 0x0f ; Condition codes are irrelevent + set_cc 0x0f ; Condition codes are irrelevant ldres @r7+,0 test_cc 1 1 1 1 test_h_gr 0x1004,r7 mvi_h_gr 0x1000,r7 - set_cc 0x0f ; Condition codes are irrelevent + set_cc 0x0f ; Condition codes are irrelevant ldres @r7+,0xf test_cc 1 1 1 1 test_h_gr 0x1004,r7 diff --git a/sim/testsuite/sim/fr30/leave.cgs b/sim/testsuite/sim/fr30/leave.cgs index 4d3dd70..225d3ed 100644 --- a/sim/testsuite/sim/fr30/leave.cgs +++ b/sim/testsuite/sim/fr30/leave.cgs @@ -14,7 +14,7 @@ leave: inci_h_gr -4,r14 mvi_h_mem 0xdeadbeef,r14 mvi_h_gr 0xbeefdead,r15 - set_cc 0x0f ; Condition codes are irrelevent + set_cc 0x0f ; Condition codes are irrelevant leave test_cc 1 1 1 1 testr_h_gr sp,r7 diff --git a/sim/testsuite/sim/fr30/nop.cgs b/sim/testsuite/sim/fr30/nop.cgs index 885c55c..10848ae 100644 --- a/sim/testsuite/sim/fr30/nop.cgs +++ b/sim/testsuite/sim/fr30/nop.cgs @@ -9,7 +9,7 @@ .global nop nop: ; Test nop - set_cc 0x0f ; Condition codes are irrelevent + set_cc 0x0f ; Condition codes are irrelevant nop test_cc 1 1 1 1 diff --git a/sim/testsuite/sim/fr30/stres.cgs b/sim/testsuite/sim/fr30/stres.cgs index a85fdf3..fd9c07e 100644 --- a/sim/testsuite/sim/fr30/stres.cgs +++ b/sim/testsuite/sim/fr30/stres.cgs @@ -11,13 +11,13 @@ stres: ; Test stres $@Ri+,$u4 ; The current implementation simply increments Ri mvi_h_gr 0x1000,r7 - set_cc 0x0f ; Condition codes are irrelevent + set_cc 0x0f ; Condition codes are irrelevant stres 0,@r7+ test_cc 1 1 1 1 test_h_gr 0x1004,r7 mvi_h_gr 0x1000,r7 - set_cc 0x0f ; Condition codes are irrelevent + set_cc 0x0f ; Condition codes are irrelevant stres 0xf,@r7+ test_cc 1 1 1 1 test_h_gr 0x1004,r7 diff --git a/sim/testsuite/sim/fr30/xchb.cgs b/sim/testsuite/sim/fr30/xchb.cgs index 3450a2e..08b8fb5 100644 --- a/sim/testsuite/sim/fr30/xchb.cgs +++ b/sim/testsuite/sim/fr30/xchb.cgs @@ -11,7 +11,7 @@ xchb: ; Test xchb @$Rj,Ri mvi_h_mem 0xdeadbeef,sp mvi_h_gr 0xbeefdead,r0 - set_cc 0x0f ; Condition codes are irrelevent + set_cc 0x0f ; Condition codes are irrelevant xchb @sp,r0 test_cc 1 1 1 1 test_h_gr 0xde,r0 diff --git a/sim/testsuite/sim/h8300/ldc.s b/sim/testsuite/sim/h8300/ldc.s index 3712a6c..56eb949 100644 --- a/sim/testsuite/sim/h8300/ldc.s +++ b/sim/testsuite/sim/h8300/ldc.s @@ -341,7 +341,7 @@ ldc_reg_sbr: mov #0xaaaaaaaa, er0 ldc er0, sbr ; set sbr to 0xaaaaaaaa - stc sbr, er1 ; retreive and check sbr value + stc sbr, er1 ; retrieve and check sbr value test_h_gr32 0xaaaaaaaa er1 test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure. @@ -358,7 +358,7 @@ ldc_reg_vbr: mov #0xaaaaaaaa, er0 ldc er0, vbr ; set sbr to 0xaaaaaaaa - stc vbr, er1 ; retreive and check sbr value + stc vbr, er1 ; retrieve and check sbr value test_h_gr32 0xaaaaaaaa er1 test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure. diff --git a/sim/testsuite/sim/h8300/stc.s b/sim/testsuite/sim/h8300/stc.s index 232bd5a..4b86ff3 100644 --- a/sim/testsuite/sim/h8300/stc.s +++ b/sim/testsuite/sim/h8300/stc.s @@ -304,7 +304,7 @@ stc_sbr_reg: mov #0xaaaaaaaa, er0 ldc er0, sbr ; set sbr to 0xaaaaaaaa - stc sbr, er1 ; retreive and check sbr value + stc sbr, er1 ; retrieve and check sbr value test_h_gr32 0xaaaaaaaa er1 test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure. @@ -321,7 +321,7 @@ stc_vbr_reg: mov #0xaaaaaaaa, er0 ldc er0, vbr ; set sbr to 0xaaaaaaaa - stc vbr, er1 ; retreive and check sbr value + stc vbr, er1 ; retrieve and check sbr value test_h_gr32 0xaaaaaaaa er1 test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure. diff --git a/sim/testsuite/sim/mips/hilo-hazard-3.s b/sim/testsuite/sim/mips/hilo-hazard-3.s index 1a0949d..e9a1595 100644 --- a/sim/testsuite/sim/mips/hilo-hazard-3.s +++ b/sim/testsuite/sim/mips/hilo-hazard-3.s @@ -1,4 +1,4 @@ -# Test for mf{hi,lo} -> mult/div/mt{hi,lo} with 2 nops inbetween. +# Test for mf{hi,lo} -> mult/div/mt{hi,lo} with 2 nops in between. # # mach: all # as: -mabi=eabi diff --git a/sim/testsuite/sim/mips/hilo-hazard-4.s b/sim/testsuite/sim/mips/hilo-hazard-4.s index 8a4c888..ba298b4 100644 --- a/sim/testsuite/sim/mips/hilo-hazard-4.s +++ b/sim/testsuite/sim/mips/hilo-hazard-4.s @@ -1,4 +1,4 @@ -# Test for mf{hi,lo} -> mult/div/mt{hi,lo} with 2 nops inbetween. +# Test for mf{hi,lo} -> mult/div/mt{hi,lo} with 2 nops in between. # # mach: all # as: -mabi=eabi -mmicromips diff --git a/sim/testsuite/sim/sh/fipr.s b/sim/testsuite/sim/sh/fipr.s index 6a949aa..50bbc5c 100644 --- a/sim/testsuite/sim/sh/fipr.s +++ b/sim/testsuite/sim/sh/fipr.s @@ -58,7 +58,7 @@ test_infp: # fr11 should be plus infinity assert_fpreg_x 0x7f800000, fr11 test_infm: - # Test negitive infinity + # Test negative infinity fldi0 fr11 mov.l infm, r0 lds r0, fpul diff --git a/zlib/contrib/inflate86/inffast.S b/zlib/contrib/inflate86/inffast.S index 2245a29..8619833 100644 --- a/zlib/contrib/inflate86/inffast.S +++ b/zlib/contrib/inflate86/inffast.S @@ -26,7 +26,7 @@ * Jan-26-2003 -- Added runtime check for MMX support with cpuid instruction. * With -DUSE_MMX, only MMX code is compiled. With -DNO_MMX, only non-MMX code * is compiled. Without either option, runtime detection is enabled. Runtime - * detection should work on all modern cpus and the recomended algorithm (flip + * detection should work on all modern cpus and the recommended algorithm (flip * ID bit on eflags and then use the cpuid instruction) is used in many * multimedia applications. Tested under win2k with gcc-2.95 and gas-2.12 * distributed with cygwin3. Compiling with gcc-2.95 -c inffast.S -o