From patchwork Tue Jul 5 13:40:28 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Antoine Tremblay X-Patchwork-Id: 13650 Received: (qmail 66645 invoked by alias); 5 Jul 2016 13:41:51 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 66578 invoked by uid 89); 5 Jul 2016 13:41:51 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=BAYES_00, SPF_PASS autolearn=ham version=3.3.2 spammy=interest X-HELO: usplmg21.ericsson.net Received: from usplmg21.ericsson.net (HELO usplmg21.ericsson.net) (198.24.6.65) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Tue, 05 Jul 2016 13:41:43 +0000 Received: from EUSAAHC008.ericsson.se (Unknown_Domain [147.117.188.96]) by usplmg21.ericsson.net (Symantec Mail Security) with SMTP id 1B.66.03614.2B8BB775; Tue, 5 Jul 2016 15:40:03 +0200 (CEST) Received: from elxa4wqvvz1.dyn.mo.ca.am.ericsson.se (147.117.188.8) by smtps-am.internal.ericsson.com (147.117.188.96) with Microsoft SMTP Server (TLS) id 14.3.294.0; Tue, 5 Jul 2016 09:40:56 -0400 From: Antoine Tremblay To: CC: Simon Marchi Subject: [PATCH v3 16/18] arm: Move insn_references_pc to common code Date: Tue, 5 Jul 2016 09:40:28 -0400 Message-ID: <1467726030-13020-17-git-send-email-antoine.tremblay@ericsson.com> In-Reply-To: <1467726030-13020-1-git-send-email-antoine.tremblay@ericsson.com> References: <1467726030-13020-1-git-send-email-antoine.tremblay@ericsson.com> MIME-Version: 1.0 X-IsSubscribed: yes From: Simon Marchi This patch moves insn_references_pc to common code in arch/, so that it can be used in gdbserver. It adds the arm_ prefix, since the function is now exported. gdb/ChangeLog: * arm-tdep.c (arm_copy_preload): Adjust to renaming. (arm_copy_preload_reg): Likewise. (arm_copy_copro_load_store): Likewise. (arm_copy_alu_imm): Likewise. (arm_copy_alu_reg): Likewise. (arm_copy_alu_shifted_reg): Likewise. (arm_copy_extra_ld_st): Likewise. (arm_copy_ldr_str_ldrb_strb): Likewise. (insn_references_pc): Move to... * arch/arm-insn-reloc.c (arm_insn_references_pc): ... here. * arch/arm-insn-reloc.h (arm_insn_references_pc): New declaraction. --- gdb/arch/arm-insn-reloc.c | 29 ++++++++++++++++++++++++++++ gdb/arch/arm-insn-reloc.h | 8 ++++++++ gdb/arm-tdep.c | 49 ++++++++--------------------------------------- 3 files changed, 45 insertions(+), 41 deletions(-) diff --git a/gdb/arch/arm-insn-reloc.c b/gdb/arch/arm-insn-reloc.c index b6ede60..7ebb507 100644 --- a/gdb/arch/arm-insn-reloc.c +++ b/gdb/arch/arm-insn-reloc.c @@ -20,6 +20,35 @@ #include "arm.h" #include "arm-insn-reloc.h" + +/* See arch/arm-insn-reloc.h. */ + +int +arm_insn_references_pc (uint32_t insn, uint32_t bitmask) +{ + uint32_t lowbit = 1; + + while (bitmask != 0) + { + uint32_t mask; + + for (; lowbit && (bitmask & lowbit) == 0; lowbit <<= 1) + ; + + if (!lowbit) + break; + + mask = lowbit * 0xf; + + if ((insn & mask) == mask) + return 1; + + bitmask &= ~mask; + } + + return 0; +} + static int arm_decode_misc_memhint_neon (uint32_t insn, struct arm_insn_reloc_visitor *visitor, diff --git a/gdb/arch/arm-insn-reloc.h b/gdb/arch/arm-insn-reloc.h index 6e83ad4..8f93214 100644 --- a/gdb/arch/arm-insn-reloc.h +++ b/gdb/arch/arm-insn-reloc.h @@ -84,6 +84,14 @@ struct thumb_16bit_insn_reloc_visitor int (*svc) (uint16_t insn, struct arm_insn_reloc_data *data); }; +/* This function is used to concisely determine if an instruction INSN + references PC. Register fields of interest in INSN should have the + corresponding fields of BITMASK set to 0b1111. The function + returns return 1 if any of these fields in INSN reference the PC + (also 0b1111, r15), else it returns 0. */ + +extern int arm_insn_references_pc (uint32_t insn, uint32_t bitmask); + extern int arm_relocate_insn (uint32_t insn, struct arm_insn_reloc_visitor *visitor, struct arm_insn_reloc_data *data); diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 2a83b82..32c81c2 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -4653,38 +4653,6 @@ displaced_write_reg (struct regcache *regs, struct displaced_step_closure *dsc, } } -/* This function is used to concisely determine if an instruction INSN - references PC. Register fields of interest in INSN should have the - corresponding fields of BITMASK set to 0b1111. The function - returns return 1 if any of these fields in INSN reference the PC - (also 0b1111, r15), else it returns 0. */ - -static int -insn_references_pc (uint32_t insn, uint32_t bitmask) -{ - uint32_t lowbit = 1; - - while (bitmask != 0) - { - uint32_t mask; - - for (; lowbit && (bitmask & lowbit) == 0; lowbit <<= 1) - ; - - if (!lowbit) - break; - - mask = lowbit * 0xf; - - if ((insn & mask) == mask) - return 1; - - bitmask &= ~mask; - } - - return 0; -} - /* The simplest copy function. Many instructions have the same effect no matter what address they are executed at: in those cases, use this. */ @@ -4773,7 +4741,7 @@ arm_copy_preload (uint32_t insn, struct arm_insn_reloc_data *data) { unsigned int rn = bits (insn, 16, 19); - if (!insn_references_pc (insn, 0x000f0000ul)) + if (!arm_insn_references_pc (insn, 0x000f0000ul)) return arm_copy_unmodified (insn, "preload", data); if (debug_displaced) @@ -4870,8 +4838,7 @@ arm_copy_preload_reg (uint32_t insn, struct arm_insn_reloc_data *data) unsigned int rn = bits (insn, 16, 19); unsigned int rm = bits (insn, 0, 3); - - if (!insn_references_pc (insn, 0x000f000ful)) + if (!arm_insn_references_pc (insn, 0x000f000ful)) return arm_copy_unmodified (insn, "preload reg", data); if (debug_displaced) @@ -4932,7 +4899,7 @@ arm_copy_copro_load_store (uint32_t insn, struct arm_insn_reloc_data *data) { unsigned int rn = bits (insn, 16, 19); - if (!insn_references_pc (insn, 0x000f0000ul)) + if (!arm_insn_references_pc (insn, 0x000f0000ul)) return arm_copy_unmodified (insn, "copro load/store", data); if (debug_displaced) @@ -5238,7 +5205,7 @@ arm_copy_alu_imm (uint32_t insn, struct arm_insn_reloc_data *data) int is_mov = (op == 0xd); ULONGEST rd_val, rn_val; - if (!insn_references_pc (insn, 0x000ff000ul)) + if (!arm_insn_references_pc (insn, 0x000ff000ul)) return arm_copy_unmodified (insn, "ALU immediate", data); if (debug_displaced) @@ -5386,7 +5353,7 @@ arm_copy_alu_reg (uint32_t insn, struct arm_insn_reloc_data *data) unsigned int op = bits (insn, 21, 24); int is_mov = (op == 0xd); - if (!insn_references_pc (insn, 0x000ff00ful)) + if (!arm_insn_references_pc (insn, 0x000ff00ful)) return arm_copy_unmodified (insn, "ALU reg", data); if (debug_displaced) @@ -5487,7 +5454,7 @@ arm_copy_alu_shifted_reg (uint32_t insn, struct arm_insn_reloc_data *data) int is_mov = (op == 0xd); unsigned int rd, rn, rm, rs; - if (!insn_references_pc (insn, 0x000fff0ful)) + if (!arm_insn_references_pc (insn, 0x000fff0ful)) return arm_copy_unmodified (insn, "ALU shifted reg", data); if (debug_displaced) @@ -5581,7 +5548,7 @@ arm_copy_extra_ld_st (uint32_t insn, struct arm_insn_reloc_data *data, struct displaced_step_closure *dsc = data->dsc; struct regcache *regs = data->regs; - if (!insn_references_pc (insn, 0x000ff00ful)) + if (!arm_insn_references_pc (insn, 0x000ff00ful)) return arm_copy_unmodified (insn, "extra load/store", data); if (debug_displaced) @@ -5812,7 +5779,7 @@ arm_copy_ldr_str_ldrb_strb (uint32_t insn, struct arm_insn_reloc_data *data, unsigned int rm = bits (insn, 0, 3); /* Only valid if !immed. */ struct displaced_step_closure *dsc = data->dsc; - if (!insn_references_pc (insn, 0x000ff00ful)) + if (!arm_insn_references_pc (insn, 0x000ff00ful)) return arm_copy_unmodified (insn, "load/store", data); if (debug_displaced)