cgen: sim: Updates to sim files to match gdb types
Commit Message
The types like MACH and MODEL have changes to SIM_MACH and SIM_MODEL
make updates to match these changes. This way people dont have to
manually update the generated files in GDB.
I am from openrisc and working on getting the openrisc sim and gdb patches
ready for submitting to upstream. This was required to get the sim build to
work.
2016-05-01 Stafford Horne <shorne@gmail.com>
* cgen/sim-cpu.scm (cgen-semantics.c, cgen-sem-switch.c): Rename
TRACE_RESULT to CGEN_TRACE_RESULT.
* cgen/sim-model.scm (gen-cpu-imp-properties): Rename
SIM_MACH_IMP_PROPERTIES to SIM_MACH_IMP_PROPERTIES.
(gen-mach-model-table): Rename MODEL to SIM_MODEL.
(gen-mach-defns): Rename MACH to SIM_MACH.
* cgen/sim.scm (op-gen-set-trace, op-gen-set-trace-parallel): Rename
TRACE_RESULT to CGEN_TRACE_RESULT.
(gen-mach-decls, gen-mach-data): Rename MACH to SIM_MACH.
cgen/sim-cpu.scm | 8 ++++----
cgen/sim-model.scm | 6 +++---
cgen/sim.scm | 8 ++++----
3 files changed, 11 insertions(+), 11 deletions(-)
Comments
On 01 May 2016 11:18, Stafford Horne wrote:
> The types like MACH and MODEL have changes to SIM_MACH and SIM_MODEL
> make updates to match these changes. This way people dont have to
> manually update the generated files in GDB.
>
> I am from openrisc and working on getting the openrisc sim and gdb patches
> ready for submitting to upstream. This was required to get the sim build to
> work.
looks fine to me (since i did make those changes in the sim), but i'm not
a cgen committer.
-mike
On 01 May 2016 15:03, Mike Frysinger wrote:
> On 01 May 2016 11:18, Stafford Horne wrote:
> > The types like MACH and MODEL have changes to SIM_MACH and SIM_MODEL
> > make updates to match these changes. This way people dont have to
> > manually update the generated files in GDB.
> >
> > I am from openrisc and working on getting the openrisc sim and gdb patches
> > ready for submitting to upstream. This was required to get the sim build to
> > work.
>
> looks fine to me (since i did make those changes in the sim), but i'm not
> a cgen committer.
i talked to Frank and i'll pick this up.
cgen is still using the CVS tree right ?
-mike
(Replying second time without the crazy text/html) sorry about that.
On Mon, 2 May 2016, Mike Frysinger wrote:
> On 01 May 2016 15:03, Mike Frysinger wrote:
>> On 01 May 2016 11:18, Stafford Horne wrote:
>>> The types like MACH and MODEL have changes to SIM_MACH and SIM_MODEL
>>> make updates to match these changes. This way people dont have to
>>> manually update the generated files in GDB.
>>>
>>> I am from openrisc and working on getting the openrisc sim and gdb patches
>>> ready for submitting to upstream. This was required to get the sim build to
>>> work.
>>
>> looks fine to me (since i did make those changes in the sim), but i'm not
>> a cgen committer.
>
> i talked to Frank and i'll pick this up.
Thank you
> cgen is still using the CVS tree right ?
Yes, as far as I know I can only find cgen in cvs. This patch is based on
the nightly release from 20160401 (I didn't have a cvs client on my
machine) so it should apply find against current CVS. Let me know if you
have any issues.
@@ -1090,8 +1090,8 @@ CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_" "attr)")
FAST_P, when desired, is defined on the command line, -DFAST_P=1. */
#if FAST_P
#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_semf_,fn)
-#undef TRACE_RESULT
-#define TRACE_RESULT(cpu, abuf, name, type, val)
+#undef CGEN_TRACE_RESULT
+#define CGEN_TRACE_RESULT(cpu, abuf, name, type, val)
#else
#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_sem_,fn)
#endif
@@ -1188,8 +1188,8 @@ CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_" "attr)")
special handlers into the instruction \"stream\". */
#if FAST_P
-#undef TRACE_RESULT
-#define TRACE_RESULT(cpu, abuf, name, type, val)
+#undef CGEN_TRACE_RESULT
+#define CGEN_TRACE_RESULT(cpu, abuf, name, type, val)
#endif
#undef GET_ATTR
@@ -16,7 +16,7 @@
"\
/* The properties of this cpu's implementation. */
-static const MACH_IMP_PROPERTIES @cpu@_imp_properties =
+static const SIM_MACH_IMP_PROPERTIES @cpu@_imp_properties =
{
sizeof (SIM_CPU),
#if WITH_SCACHE
@@ -249,7 +249,7 @@ static const MACH_IMP_PROPERTIES @cpu@_imp_properties =
(define (/gen-mach-model-table mach)
(string-list
"\
-static const MODEL " (gen-sym mach) "_models[] =\n{\n"
+static const SIM_MODEL " (gen-sym mach) "_models[] =\n{\n"
(string-list-map (lambda (model)
(string-list " { "
"\"" (obj:str-name model) "\", "
@@ -343,7 +343,7 @@ static void\n"
#endif
}
-const MACH " (gen-sym mach) "_mach =
+const SIM_MACH " (gen-sym mach) "_mach =
{
\"" (obj:str-name mach) "\", "
"\"" (mach-bfd-name mach) "\", "
@@ -1265,7 +1265,7 @@
; operand instance table].
; Could just scan the operand table for the operand or hardware number,
; assuming the operand number is stored in `op'.
- " TRACE_RESULT (current_cpu, abuf"
+ " CGEN_TRACE_RESULT (current_cpu, abuf"
", " (send op 'gen-pretty-name mode)
", " (mode:printf-type mode)
", opval);\n"
@@ -1292,7 +1292,7 @@
; operand instance table].
; Could just scan the operand table for the operand or hardware number,
; assuming the operand number is stored in `op'.
- " TRACE_RESULT (current_cpu, abuf"
+ " CGEN_TRACE_RESULT (current_cpu, abuf"
", " (send op 'gen-pretty-name mode)
", " (mode:printf-type mode)
", opval);\n"
@@ -1464,7 +1464,7 @@
(string-append
(string-map (lambda (mach)
(gen-obj-sanitize mach
- (string-append "extern const MACH "
+ (string-append "extern const SIM_MACH "
(gen-sym mach)
"_mach;\n")))
(current-mach-list))
@@ -1475,7 +1475,7 @@
(define (/gen-mach-data)
(string-append
- "const MACH *sim_machs[] =\n{\n"
+ "const SIM_MACH *sim_machs[] =\n{\n"
(string-map (lambda (mach)
(gen-obj-sanitize
mach