From patchwork Fri Mar 4 16:02:59 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yao Qi X-Patchwork-Id: 11195 Received: (qmail 40487 invoked by alias); 4 Mar 2016 16:03:11 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 40464 invoked by uid 89); 4 Mar 2016 16:03:09 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 spammy=Hx-languages-length:2373 X-HELO: mail-pa0-f45.google.com Received: from mail-pa0-f45.google.com (HELO mail-pa0-f45.google.com) (209.85.220.45) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Fri, 04 Mar 2016 16:03:06 +0000 Received: by mail-pa0-f45.google.com with SMTP id fi3so35041088pac.3 for ; Fri, 04 Mar 2016 08:03:06 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:subject:date:message-id; bh=RvcMaNVE2FPvHGUlfF4X5BUGYePWetz5Qg7ybmOrpkc=; b=mL2HXXF4B0w4X8IcH+srFyD/LFXAkLBjJHXLubvUH6r+VMyWrspm6fvZqchmKoG3cZ kbbgoRbE4aFOoZRaczFvF+ot+94kLPwXepLwWaNoT+Q3K4fMhPBLHKiOcb9pIAlRAU1h Re9En6WUq65pGqFCclqIs+u42lHtx17gw8gjiB19IcqDiCLsSm7X8msRTu/nqxHHT4Sp wb+BdEzggx2n1wtiDqIxy4ohCqOeA7DJ+UAAW/ed+U/o0FhsrLxzuvOXWth2cwwVXSm/ 8nA3CBwjXESv+OZddG5NQZbqzuIcv4fLU4+5T6BXiclrgnv69LMz5stq5biQDqvTsZgF IF6w== X-Gm-Message-State: AD7BkJK7tSqdbOg7V0fOoSW56Gn11FOkj/aE7nejFWfK5Q69N1S/cUGYDOGIBOCYn/Picw== X-Received: by 10.66.218.196 with SMTP id pi4mr12998507pac.147.1457107384720; Fri, 04 Mar 2016 08:03:04 -0800 (PST) Received: from E107787-LIN.cambridge.arm.com (gcc1-power7.osuosl.org. [140.211.15.137]) by smtp.gmail.com with ESMTPSA id 144sm6488105pfa.83.2016.03.04.08.03.03 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 04 Mar 2016 08:03:04 -0800 (PST) From: Yao Qi X-Google-Original-From: Yao Qi To: gdb-patches@sourceware.org Subject: [PATCH] ARM process record: VMOV Date: Fri, 4 Mar 2016 16:02:59 +0000 Message-Id: <1457107379-18996-1-git-send-email-yao.qi@linaro.org> X-IsSubscribed: yes ARM process record gets the wrong register number for VMOV (from core register to single-precision register). That is, we should record the D register rather than the S pseudo register. The patch also removes the condition "bit (arm_insn_r->arm_insn, 20)" check, which has been checked above. It fixes the following internal error, (gdb) PASS: gdb.reverse/finish-precsave.exp: BP at end of main continue^M Continuing.^M ../../binutils-gdb/gdb/regcache.c:649: internal-error: regcache_raw_read: Assertion `regnum >= 0 && regnum < regcache->descr->nr_raw_registers' failed.^M A problem internal to GDB has been detected,FAIL: gdb.reverse/finish-precsave.exp: run to end of main (GDB internal error) I'll push it in. gdb: 2016-03-04 Yao Qi * arm-tdep.c (arm_record_vdata_transfer_insn): Simplify the condition check. Record the right D register number. --- gdb/ChangeLog | 5 +++++ gdb/arm-tdep.c | 13 ++----------- 2 files changed, 7 insertions(+), 11 deletions(-) diff --git a/gdb/ChangeLog b/gdb/ChangeLog index 773a9e6..7f37014 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,5 +1,10 @@ 2016-03-04 Yao Qi + * arm-tdep.c (arm_record_vdata_transfer_insn): Simplify the + condition check. Record the right D register number. + +2016-03-04 Yao Qi + * arm-tdep.c (arm_record_extension_space): Remove code printing "Process record does not support". (arm_record_data_proc_misc_ld_str): Likewise. diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 605f09b..54a21ef 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -10800,12 +10800,7 @@ arm_record_vdata_transfer_insn (insn_decode_record *arm_insn_r) /* Handle VMOV instruction. */ if (bits_a == 0x00) { - if (bit (arm_insn_r->arm_insn, 20)) - record_buf[0] = reg_t; - else - record_buf[0] = num_regs + (bit (arm_insn_r->arm_insn, 7) | - (reg_v << 1)); - + record_buf[0] = reg_t; arm_insn_r->reg_rec_count = 1; } /* Handle VMRS instruction. */ @@ -10823,11 +10818,7 @@ arm_record_vdata_transfer_insn (insn_decode_record *arm_insn_r) /* Handle VMOV instruction. */ if (bits_a == 0x00) { - if (bit (arm_insn_r->arm_insn, 20)) - record_buf[0] = reg_t; - else - record_buf[0] = num_regs + (bit (arm_insn_r->arm_insn, 7) | - (reg_v << 1)); + record_buf[0] = ARM_D0_REGNUM + reg_v; arm_insn_r->reg_rec_count = 1; }