From patchwork Fri Jan 8 18:32:28 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luis Machado X-Patchwork-Id: 10297 Received: (qmail 125322 invoked by alias); 8 Jan 2016 18:32:38 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 125288 invoked by uid 89); 8 Jan 2016 18:32:36 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.1 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=core-file, Fill, UD:gdb.arch, gdb.arch X-HELO: relay1.mentorg.com Received: from relay1.mentorg.com (HELO relay1.mentorg.com) (192.94.38.131) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 08 Jan 2016 18:32:35 +0000 Received: from svr-orw-fem-03.mgc.mentorg.com ([147.34.97.39]) by relay1.mentorg.com with esmtp id 1aHbpw-0001Ta-Jr from Luis_Gustavo@mentor.com ; Fri, 08 Jan 2016 10:32:32 -0800 Received: from opsys.world.mentorg.com (147.34.91.1) by svr-orw-fem-03.mgc.mentorg.com (147.34.97.39) with Microsoft SMTP Server id 14.3.224.2; Fri, 8 Jan 2016 10:32:31 -0800 From: Luis Machado To: CC: , Subject: [PATCH] Handle loading improper core files gracefully in the mips backend. Date: Fri, 8 Jan 2016 16:32:28 -0200 Message-ID: <1452277948-25292-1-git-send-email-lgustavo@codesourcery.com> MIME-Version: 1.0 X-IsSubscribed: yes bz 18964 was reported as a internal error from the mips backend when running gdb.arch/i386-biarch-core.exp. The backend gets confused and ends up picking up an invalid combination of 32-bit ISA and 64-bit ABI, resulting, later on, in an unexpected mismatch between the raw register size for PC (4) and the pseudo register size for PC (8). The point that makes the architecture selection go south is when we notice the core file is 64-bit, so we go with MIPS_ABI_N64, but we are using MIPS16 as the ISA. The attached patch adds a bit more logic to the incompatibility check during the architecture initialization. It doesn't completely solve the problem with this testcase though, but it gets rid of an ugly internal error and changes things from this: FAIL: gdb.arch/i386-biarch-core.exp: core-file (GDB internal error) === gdb Summary === to this: FAIL: gdb.arch/i386-biarch-core.exp: .text is readable === gdb Summary === Leaving this failure behind: x/bx 0x400078^M 0x400078: Cannot access memory at address 0x400078^M (gdb) FAIL: gdb.arch/i386-biarch-core.exp: .text is readable It is not clear to me what is expected of this particular test when executed for a non-x86 target. In any case, hardening of the mips backend seems to be an improvement already. Maciej, do you have more input on additional incompatibilities that we need to check for? gdb/ChangeLog: 2016-01-08 Luis Machado bz 18964 * mips-tdep.c (mips_gdbarch_init): Handle additional incompatible ISA/ABI pairs gracefully and return. --- gdb/mips-tdep.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/gdb/mips-tdep.c b/gdb/mips-tdep.c index c8e12e8..9bdcf96 100644 --- a/gdb/mips-tdep.c +++ b/gdb/mips-tdep.c @@ -8206,6 +8206,8 @@ mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) enum mips_isa mips_isa; int dspacc; int dspctl; + /* Whether we have an unknown/unsuitable architecture description. */ + int arch_is_incompatible = 0; /* Fill in the OS dependent register numbers and names. */ if (info.osabi == GDB_OSABI_IRIX) @@ -8571,11 +8573,16 @@ mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) /* If we have only 32-bit registers, then we can't debug a 64-bit ABI. */ - if (info.target_desc - && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL - && mips_abi != MIPS_ABI_EABI32 - && mips_abi != MIPS_ABI_O32) + if (mips_abi != MIPS_ABI_EABI32 && mips_abi != MIPS_ABI_O32 + && ((info.target_desc + && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL) + || mips_isa == ISA_MIPS16)) + arch_is_incompatible = 1; + + if (arch_is_incompatible) { + /* This is an unsuitable combination of ABI/ISA. Just cleanup and + return. */ if (tdesc_data != NULL) tdesc_data_cleanup (tdesc_data); return NULL;