From patchwork Sun Nov 15 13:16:50 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Frysinger X-Patchwork-Id: 9669 X-Patchwork-Delegate: vapier@gentoo.org Received: (qmail 37706 invoked by alias); 15 Nov 2015 13:17:00 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 37548 invoked by uid 89); 15 Nov 2015 13:17:00 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.1 required=5.0 tests=AWL, BAYES_00, RP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 X-HELO: smtp.gentoo.org Received: from smtp.gentoo.org (HELO smtp.gentoo.org) (140.211.166.183) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Sun, 15 Nov 2015 13:16:57 +0000 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.gentoo.org (Postfix) with ESMTP id DFD4C340712 for ; Sun, 15 Nov 2015 13:16:55 +0000 (UTC) From: Mike Frysinger To: gdb-patches@sourceware.org Subject: [PATCH 3/4] sim: mcore: switch to common sim-reg [committed] Date: Sun, 15 Nov 2015 08:16:50 -0500 Message-Id: <1447593411-32516-3-git-send-email-vapier@gentoo.org> In-Reply-To: <1447593411-32516-1-git-send-email-vapier@gentoo.org> References: <1447593411-32516-1-git-send-email-vapier@gentoo.org> X-IsSubscribed: yes This is not entirely useful as mcore doesn't (yet) store its register state in the cpu state, but it does allow for switching to the common code for these functions. --- sim/mcore/ChangeLog | 9 +++++++++ sim/mcore/Makefile.in | 1 + sim/mcore/interp.c | 10 ++++++---- 3 files changed, 16 insertions(+), 4 deletions(-) diff --git a/sim/mcore/ChangeLog b/sim/mcore/ChangeLog index af698e0..d89050d 100644 --- a/sim/mcore/ChangeLog +++ b/sim/mcore/ChangeLog @@ -1,5 +1,14 @@ 2015-11-15 Mike Frysinger + * Makefile.in (SIM_OBJS): Add sim-reg.o. + * interp.c (sim_store_register): Rename to ... + (mcore_reg_store): ... this. Change SIM_DESC to SIM_CPU. + (sim_fetch_register): Rename to ... + (mcore_reg_fetch): ... this. Change SIM_DESC to SIM_CPU. + (sim_open): Call CPU_REG_FETCH and CPU_REG_STORE. + +2015-11-15 Mike Frysinger + * Makefile.in (SIM_OBJS): Add sim-reason.o and sim-resume.o. * interp.c (struct mcore_regset): Delete exception. (util): Add SIM_DESC and SIM_CPU args. Call sim_engine_halt instead diff --git a/sim/mcore/Makefile.in b/sim/mcore/Makefile.in index c66e568..8e84b0e 100644 --- a/sim/mcore/Makefile.in +++ b/sim/mcore/Makefile.in @@ -25,6 +25,7 @@ SIM_OBJS = \ $(SIM_NEW_COMMON_OBJS) \ sim-hload.o \ sim-reason.o \ + sim-reg.o \ sim-resume.o \ sim-stop.o diff --git a/sim/mcore/interp.c b/sim/mcore/interp.c index 7009f00..6972b7f 100644 --- a/sim/mcore/interp.c +++ b/sim/mcore/interp.c @@ -1285,8 +1285,8 @@ sim_engine_run (SIM_DESC sd, } } -int -sim_store_register (SIM_DESC sd, int rn, unsigned char *memory, int length) +static int +mcore_reg_store (SIM_CPU *scpu, int rn, unsigned char *memory, int length) { if (rn < NUM_MCORE_REGS && rn >= 0) { @@ -1305,8 +1305,8 @@ sim_store_register (SIM_DESC sd, int rn, unsigned char *memory, int length) return 0; } -int -sim_fetch_register (SIM_DESC sd, int rn, unsigned char *memory, int length) +static int +mcore_reg_fetch (SIM_CPU *scpu, int rn, unsigned char *memory, int length) { if (rn < NUM_MCORE_REGS && rn >= 0) { @@ -1447,6 +1447,8 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb, struct bfd *abfd, char **argv) { SIM_CPU *cpu = STATE_CPU (sd, i); + CPU_REG_FETCH (cpu) = mcore_reg_fetch; + CPU_REG_STORE (cpu) = mcore_reg_store; CPU_PC_FETCH (cpu) = mcore_pc_get; CPU_PC_STORE (cpu) = mcore_pc_set;