From patchwork Wed Oct 7 09:26:23 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yao Qi X-Patchwork-Id: 8965 Received: (qmail 2360 invoked by alias); 7 Oct 2015 09:27:01 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 2303 invoked by uid 89); 7 Oct 2015 09:27:01 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.2 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-pa0-f46.google.com Received: from mail-pa0-f46.google.com (HELO mail-pa0-f46.google.com) (209.85.220.46) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Wed, 07 Oct 2015 09:26:47 +0000 Received: by pablk4 with SMTP id lk4so16260088pab.3 for ; Wed, 07 Oct 2015 02:26:45 -0700 (PDT) X-Received: by 10.68.200.167 with SMTP id jt7mr49579872pbc.83.1444210005394; Wed, 07 Oct 2015 02:26:45 -0700 (PDT) Received: from E107787-LIN.cambridge.arm.com (power-aix.osuosl.org. [140.211.15.154]) by smtp.gmail.com with ESMTPSA id xa4sm38490858pac.28.2015.10.07.02.26.44 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 07 Oct 2015 02:26:45 -0700 (PDT) From: Yao Qi X-Google-Original-From: Yao Qi To: gdb-patches@sourceware.org Subject: [PATCH 09/11] Rename emit_insn to aarch64_emit_insn Date: Wed, 7 Oct 2015 10:26:23 +0100 Message-Id: <1444209985-15829-10-git-send-email-yao.qi@linaro.org> In-Reply-To: <1444209985-15829-1-git-send-email-yao.qi@linaro.org> References: <1444209985-15829-1-git-send-email-yao.qi@linaro.org> X-IsSubscribed: yes As emit_insn becomes extern, the prefix "aarch64_" is needed. This patch renames emit_insn to aarch64_emit_insn. gdb: 2015-10-05 Yao Qi * arch/aarch64-insn.c (emit_insn): Rename to ... (aarch64_emit_insn): ... it. All callers updated. gdb/gdbserver: 2015-10-05 Yao Qi * linux-aarch64-low.c: Update all callers of function renaming from emit_insn to aarch64_emit_insn. --- gdb/aarch64-tdep.c | 2 +- gdb/arch/aarch64-insn.c | 25 ++++++------ gdb/arch/aarch64-insn.h | 40 ++++++++++---------- gdb/gdbserver/linux-aarch64-low.c | 80 ++++++++++++++++++++------------------- 4 files changed, 75 insertions(+), 72 deletions(-) diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c index d9c4334..243f0f5 100644 --- a/gdb/aarch64-tdep.c +++ b/gdb/aarch64-tdep.c @@ -2771,7 +2771,7 @@ aarch64_displaced_step_others (const uint32_t insn, struct aarch64_displaced_step_data *dsd = (struct aarch64_displaced_step_data *) data; - emit_insn (dsd->insn_buf, insn); + aarch64_emit_insn (dsd->insn_buf, insn); dsd->insn_count = 1; if ((insn & 0xfffffc1f) == 0xd65f0000) diff --git a/gdb/arch/aarch64-insn.c b/gdb/arch/aarch64-insn.c index 3bc0117..99f4fb9 100644 --- a/gdb/arch/aarch64-insn.c +++ b/gdb/arch/aarch64-insn.c @@ -333,7 +333,7 @@ aarch64_relocate_instruction (uint32_t insn, instructions written (aka. 1). */ int -emit_insn (uint32_t *buf, uint32_t insn) +aarch64_emit_insn (uint32_t *buf, uint32_t insn) { *buf = insn; return 1; @@ -356,10 +356,10 @@ emit_load_store (uint32_t *buf, uint32_t size, { op = ENCODE (1, 1, 24); - return emit_insn (buf, opcode | ENCODE (size, 2, 30) | op - | ENCODE (operand.index >> 3, 12, 10) - | ENCODE (rn.num, 5, 5) - | ENCODE (rt.num, 5, 0)); + return aarch64_emit_insn (buf, opcode | ENCODE (size, 2, 30) | op + | ENCODE (operand.index >> 3, 12, 10) + | ENCODE (rn.num, 5, 5) + | ENCODE (rt.num, 5, 0)); } case MEMORY_OPERAND_POSTINDEX: { @@ -367,9 +367,10 @@ emit_load_store (uint32_t *buf, uint32_t size, op = ENCODE (0, 1, 24); - return emit_insn (buf, opcode | ENCODE (size, 2, 30) | op - | post_index | ENCODE (operand.index, 9, 12) - | ENCODE (rn.num, 5, 5) | ENCODE (rt.num, 5, 0)); + return aarch64_emit_insn (buf, opcode | ENCODE (size, 2, 30) | op + | post_index | ENCODE (operand.index, 9, 12) + | ENCODE (rn.num, 5, 5) + | ENCODE (rt.num, 5, 0)); } case MEMORY_OPERAND_PREINDEX: { @@ -377,10 +378,10 @@ emit_load_store (uint32_t *buf, uint32_t size, op = ENCODE (0, 1, 24); - return emit_insn (buf, opcode | ENCODE (size, 2, 30) | op - | pre_index | ENCODE (operand.index, 9, 12) - | ENCODE (rn.num, 5, 5) - | ENCODE (rt.num, 5, 0)); + return aarch64_emit_insn (buf, opcode | ENCODE (size, 2, 30) | op + | pre_index | ENCODE (operand.index, 9, 12) + | ENCODE (rn.num, 5, 5) + | ENCODE (rt.num, 5, 0)); } default: return 0; diff --git a/gdb/arch/aarch64-insn.h b/gdb/arch/aarch64-insn.h index 01a5d73..37ef37e 100644 --- a/gdb/arch/aarch64-insn.h +++ b/gdb/arch/aarch64-insn.h @@ -223,7 +223,7 @@ void aarch64_relocate_instruction (uint32_t insn, +/- 128MB (26 bits << 2). */ #define emit_b(buf, is_bl, offset) \ - emit_insn (buf, ((is_bl) ? BL : B) | (ENCODE ((offset) >> 2, 26, 0))) + aarch64_emit_insn (buf, ((is_bl) ? BL : B) | (ENCODE ((offset) >> 2, 26, 0))) /* Write a BCOND instruction into *BUF. @@ -234,10 +234,10 @@ void aarch64_relocate_instruction (uint32_t insn, byte-addressed but should be 4 bytes aligned. It has a limited range of +/- 1MB (19 bits << 2). */ -#define emit_bcond(buf, cond, offset) \ - emit_insn (buf, \ - BCOND | ENCODE ((offset) >> 2, 19, 5) \ - | ENCODE ((cond), 4, 0)) +#define emit_bcond(buf, cond, offset) \ + aarch64_emit_insn (buf, \ + BCOND | ENCODE ((offset) >> 2, 19, 5) \ + | ENCODE ((cond), 4, 0)) /* Write a CBZ or CBNZ instruction into *BUF. @@ -250,12 +250,12 @@ void aarch64_relocate_instruction (uint32_t insn, byte-addressed but should be 4 bytes aligned. It has a limited range of +/- 1MB (19 bits << 2). */ -#define emit_cb(buf, is_cbnz, rt, offset) \ - emit_insn (buf, \ - ((is_cbnz) ? CBNZ : CBZ) \ - | ENCODE (rt.is64, 1, 31) /* sf */ \ - | ENCODE (offset >> 2, 19, 5) /* imm19 */ \ - | ENCODE (rt.num, 5, 0)) +#define emit_cb(buf, is_cbnz, rt, offset) \ + aarch64_emit_insn (buf, \ + ((is_cbnz) ? CBNZ : CBZ) \ + | ENCODE (rt.is64, 1, 31) /* sf */ \ + | ENCODE (offset >> 2, 19, 5) /* imm19 */ \ + | ENCODE (rt.num, 5, 0)) /* Write a LDR instruction into *BUF. @@ -298,19 +298,19 @@ void aarch64_relocate_instruction (uint32_t insn, byte-addressed but should be 4 bytes aligned. It has a limited range of +/- 32KB (14 bits << 2). */ -#define emit_tb(buf, is_tbnz, bit, rt, offset) \ - emit_insn (buf, \ - ((is_tbnz) ? TBNZ: TBZ) \ - | ENCODE (bit >> 5, 1, 31) /* b5 */ \ - | ENCODE (bit, 5, 19) /* b40 */ \ - | ENCODE (offset >> 2, 14, 5) /* imm14 */ \ - | ENCODE (rt.num, 5, 0)) +#define emit_tb(buf, is_tbnz, bit, rt, offset) \ + aarch64_emit_insn (buf, \ + ((is_tbnz) ? TBNZ: TBZ) \ + | ENCODE (bit >> 5, 1, 31) /* b5 */ \ + | ENCODE (bit, 5, 19) /* b40 */ \ + | ENCODE (offset >> 2, 14, 5) /* imm14 */ \ + | ENCODE (rt.num, 5, 0)) /* Write a NOP instruction into *BUF. */ -#define emit_nop(buf) emit_insn (buf, NOP) +#define emit_nop(buf) aarch64_emit_insn (buf, NOP) -int emit_insn (uint32_t *buf, uint32_t insn); +int aarch64_emit_insn (uint32_t *buf, uint32_t insn); int emit_load_store (uint32_t *buf, uint32_t size, enum aarch64_opcodes opcode, diff --git a/gdb/gdbserver/linux-aarch64-low.c b/gdb/gdbserver/linux-aarch64-low.c index 9450449..963511b 100644 --- a/gdb/gdbserver/linux-aarch64-low.c +++ b/gdb/gdbserver/linux-aarch64-low.c @@ -743,7 +743,7 @@ enum aarch64_system_control_registers static int emit_blr (uint32_t *buf, struct aarch64_register rn) { - return emit_insn (buf, BLR | ENCODE (rn.num, 5, 5)); + return aarch64_emit_insn (buf, BLR | ENCODE (rn.num, 5, 5)); } /* Write a RET instruction into *BUF. @@ -755,7 +755,7 @@ emit_blr (uint32_t *buf, struct aarch64_register rn) static int emit_ret (uint32_t *buf, struct aarch64_register rn) { - return emit_insn (buf, RET | ENCODE (rn.num, 5, 5)); + return aarch64_emit_insn (buf, RET | ENCODE (rn.num, 5, 5)); } static int @@ -798,10 +798,10 @@ emit_load_store_pair (uint32_t *buf, enum aarch64_opcodes opcode, return 0; } - return emit_insn (buf, opcode | opc | pre_index | write_back - | ENCODE (operand.index >> 3, 7, 15) - | ENCODE (rt2.num, 5, 10) - | ENCODE (rn.num, 5, 5) | ENCODE (rt.num, 5, 0)); + return aarch64_emit_insn (buf, opcode | opc | pre_index | write_back + | ENCODE (operand.index >> 3, 7, 15) + | ENCODE (rt2.num, 5, 10) + | ENCODE (rn.num, 5, 5) | ENCODE (rt.num, 5, 0)); } /* Write a STP instruction into *BUF. @@ -858,9 +858,10 @@ emit_ldp_q_offset (uint32_t *buf, unsigned rt, unsigned rt2, uint32_t opc = ENCODE (2, 2, 30); uint32_t pre_index = ENCODE (1, 1, 24); - return emit_insn (buf, LDP_SIMD_VFP | opc | pre_index - | ENCODE (offset >> 4, 7, 15) | ENCODE (rt2, 5, 10) - | ENCODE (rn.num, 5, 5) | ENCODE (rt, 5, 0)); + return aarch64_emit_insn (buf, LDP_SIMD_VFP | opc | pre_index + | ENCODE (offset >> 4, 7, 15) + | ENCODE (rt2, 5, 10) + | ENCODE (rn.num, 5, 5) | ENCODE (rt, 5, 0)); } /* Write a STP (SIMD&VFP) instruction using Q registers into *BUF. @@ -879,7 +880,7 @@ emit_stp_q_offset (uint32_t *buf, unsigned rt, unsigned rt2, uint32_t opc = ENCODE (2, 2, 30); uint32_t pre_index = ENCODE (1, 1, 24); - return emit_insn (buf, STP_SIMD_VFP | opc | pre_index + return aarch64_emit_insn (buf, STP_SIMD_VFP | opc | pre_index | ENCODE (offset >> 4, 7, 15) | ENCODE (rt2, 5, 10) | ENCODE (rn.num, 5, 5) | ENCODE (rt, 5, 0)); @@ -954,9 +955,9 @@ emit_load_store_exclusive (uint32_t *buf, uint32_t size, struct aarch64_register rt2, struct aarch64_register rn) { - return emit_insn (buf, opcode | ENCODE (size, 2, 30) - | ENCODE (rs.num, 5, 16) | ENCODE (rt2.num, 5, 10) - | ENCODE (rn.num, 5, 5) | ENCODE (rt.num, 5, 0)); + return aarch64_emit_insn (buf, opcode | ENCODE (size, 2, 30) + | ENCODE (rs.num, 5, 16) | ENCODE (rt2.num, 5, 10) + | ENCODE (rn.num, 5, 5) | ENCODE (rt.num, 5, 0)); } /* Write a LAXR instruction into *BUF. @@ -1015,8 +1016,8 @@ emit_data_processing_reg (uint32_t *buf, enum aarch64_opcodes opcode, { uint32_t size = ENCODE (rd.is64, 1, 31); - return emit_insn (buf, opcode | size | ENCODE (rm.num, 5, 16) - | ENCODE (rn.num, 5, 5) | ENCODE (rd.num, 5, 0)); + return aarch64_emit_insn (buf, opcode | size | ENCODE (rm.num, 5, 16) + | ENCODE (rn.num, 5, 5) | ENCODE (rd.num, 5, 0)); } /* Helper function for data processing instructions taking either a register @@ -1037,9 +1038,10 @@ emit_data_processing (uint32_t *buf, enum aarch64_opcodes opcode, /* xxx1 000x xxxx xxxx xxxx xxxx xxxx xxxx */ operand_opcode = ENCODE (8, 4, 25); - return emit_insn (buf, opcode | operand_opcode | size - | ENCODE (operand.imm, 12, 10) - | ENCODE (rn.num, 5, 5) | ENCODE (rd.num, 5, 0)); + return aarch64_emit_insn (buf, opcode | operand_opcode | size + | ENCODE (operand.imm, 12, 10) + | ENCODE (rn.num, 5, 5) + | ENCODE (rd.num, 5, 0)); } else { @@ -1112,9 +1114,9 @@ emit_mov (uint32_t *buf, struct aarch64_register rd, /* Do not shift the immediate. */ uint32_t shift = ENCODE (0, 2, 21); - return emit_insn (buf, MOV | size | shift - | ENCODE (operand.imm, 16, 5) - | ENCODE (rd.num, 5, 0)); + return aarch64_emit_insn (buf, MOV | size | shift + | ENCODE (operand.imm, 16, 5) + | ENCODE (rd.num, 5, 0)); } else return emit_add (buf, rd, operand.reg, immediate_operand (0)); @@ -1134,8 +1136,8 @@ emit_movk (uint32_t *buf, struct aarch64_register rd, uint32_t imm, { uint32_t size = ENCODE (rd.is64, 1, 31); - return emit_insn (buf, MOVK | size | ENCODE (shift, 2, 21) | - ENCODE (imm, 16, 5) | ENCODE (rd.num, 5, 0)); + return aarch64_emit_insn (buf, MOVK | size | ENCODE (shift, 2, 21) | + ENCODE (imm, 16, 5) | ENCODE (rd.num, 5, 0)); } /* Write instructions into *BUF in order to move ADDR into a register. @@ -1343,8 +1345,8 @@ static int emit_mrs (uint32_t *buf, struct aarch64_register rt, enum aarch64_system_control_registers system_reg) { - return emit_insn (buf, MRS | ENCODE (system_reg, 15, 5) - | ENCODE (rt.num, 5, 0)); + return aarch64_emit_insn (buf, MRS | ENCODE (system_reg, 15, 5) + | ENCODE (rt.num, 5, 0)); } /* Write a MSR instruction into *BUF. The register size is 64-bit. @@ -1358,8 +1360,8 @@ static int emit_msr (uint32_t *buf, enum aarch64_system_control_registers system_reg, struct aarch64_register rt) { - return emit_insn (buf, MSR | ENCODE (system_reg, 15, 5) - | ENCODE (rt.num, 5, 0)); + return aarch64_emit_insn (buf, MSR | ENCODE (system_reg, 15, 5) + | ENCODE (rt.num, 5, 0)); } /* Write a SEVL instruction into *BUF. @@ -1369,7 +1371,7 @@ emit_msr (uint32_t *buf, enum aarch64_system_control_registers system_reg, static int emit_sevl (uint32_t *buf) { - return emit_insn (buf, SEVL); + return aarch64_emit_insn (buf, SEVL); } /* Write a WFE instruction into *BUF. @@ -1379,7 +1381,7 @@ emit_sevl (uint32_t *buf) static int emit_wfe (uint32_t *buf) { - return emit_insn (buf, WFE); + return aarch64_emit_insn (buf, WFE); } /* Write a SBFM instruction into *BUF. @@ -1401,9 +1403,9 @@ emit_sbfm (uint32_t *buf, struct aarch64_register rd, uint32_t size = ENCODE (rd.is64, 1, 31); uint32_t n = ENCODE (rd.is64, 1, 22); - return emit_insn (buf, SBFM | size | n | ENCODE (immr, 6, 16) - | ENCODE (imms, 6, 10) | ENCODE (rn.num, 5, 5) - | ENCODE (rd.num, 5, 0)); + return aarch64_emit_insn (buf, SBFM | size | n | ENCODE (immr, 6, 16) + | ENCODE (imms, 6, 10) | ENCODE (rn.num, 5, 5) + | ENCODE (rd.num, 5, 0)); } /* Write a SBFX instruction into *BUF. @@ -1446,9 +1448,9 @@ emit_ubfm (uint32_t *buf, struct aarch64_register rd, uint32_t size = ENCODE (rd.is64, 1, 31); uint32_t n = ENCODE (rd.is64, 1, 22); - return emit_insn (buf, UBFM | size | n | ENCODE (immr, 6, 16) - | ENCODE (imms, 6, 10) | ENCODE (rn.num, 5, 5) - | ENCODE (rd.num, 5, 0)); + return aarch64_emit_insn (buf, UBFM | size | n | ENCODE (immr, 6, 16) + | ENCODE (imms, 6, 10) | ENCODE (rn.num, 5, 5) + | ENCODE (rd.num, 5, 0)); } /* Write a UBFX instruction into *BUF. @@ -1490,9 +1492,9 @@ emit_csinc (uint32_t *buf, struct aarch64_register rd, { uint32_t size = ENCODE (rd.is64, 1, 31); - return emit_insn (buf, CSINC | size | ENCODE (rm.num, 5, 16) - | ENCODE (cond, 4, 12) | ENCODE (rn.num, 5, 5) - | ENCODE (rd.num, 5, 0)); + return aarch64_emit_insn (buf, CSINC | size | ENCODE (rm.num, 5, 16) + | ENCODE (cond, 4, 12) | ENCODE (rn.num, 5, 5) + | ENCODE (rd.num, 5, 0)); } /* Write a CSET instruction into *BUF. @@ -1757,7 +1759,7 @@ aarch64_ftrace_insn_reloc_others (const uint32_t insn, /* The instruction is not PC relative. Just re-emit it at the new location. */ - insn_reloc->insn_ptr += emit_insn (insn_reloc->insn_ptr, insn); + insn_reloc->insn_ptr += aarch64_emit_insn (insn_reloc->insn_ptr, insn); } static const struct aarch64_insn_visitor visitor =