From patchwork Tue Feb 17 07:44:40 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiri Gaisler X-Patchwork-Id: 5104 Received: (qmail 31876 invoked by alias); 17 Feb 2015 07:45:29 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 31763 invoked by uid 89); 17 Feb 2015 07:45:28 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.1 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.2 X-HELO: bin-vsp-out-01.atm.binero.net Received: from vsp-unauthed01.binero.net (HELO bin-vsp-out-01.atm.binero.net) (195.74.38.225) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Tue, 17 Feb 2015 07:45:27 +0000 X-Halon-ID: f86b48ca-b678-11e4-acbf-005056917a89 Authorized-sender: jiri@gaisler.se Received: from vaio.orange-hotspot.com (unknown [81.253.22.86]) by bin-vsp-out-01.atm.binero.net (Halon Mail Gateway) with ESMTPSA; Tue, 17 Feb 2015 08:45:40 +0100 (CET) From: Jiri Gaisler To: gdb-patches@sourceware.org Cc: Jiri Gaisler Subject: [PATCH 03/23] sim/erc32: Perform pseudo-init of system if binary starts from non-zero address. Date: Tue, 17 Feb 2015 08:44:40 +0100 Message-Id: <1424159099-5148-4-git-send-email-jiri@gaisler.se> In-Reply-To: <1424159099-5148-1-git-send-email-jiri@gaisler.se> References: <1424159099-5148-1-git-send-email-jiri@gaisler.se> Binaries produced by most erc32 tool-chains do not include system initialization. sis will detect this and initialize necessary registers for memory and timer control. * erc32.c (mec_read) allow simulator memory size to be read by application. (boot_init) initialize memory and timers if start address is not 0. * erc32,c (exe_cmd) call boot_init if start address not 0 * interf.c (run_sim) Likewise --- sim/erc32/erc32.c | 24 ++++++++++++++++++++++++ sim/erc32/func.c | 1 + sim/erc32/interf.c | 1 + 3 files changed, 26 insertions(+) diff --git a/sim/erc32/erc32.c b/sim/erc32/erc32.c index 4d4177e..4fa8f61 100644 --- a/sim/erc32/erc32.c +++ b/sim/erc32/erc32.c @@ -743,6 +743,14 @@ mec_read(addr, asi, data) *data = read_uart(addr); break; + case 0xF4: /* simulator RAM size in bytes */ + *data = 4096*1024; + break; + + case 0xF8: /* simulator ROM size in bytes */ + *data = 1024*1024; + break; + default: set_sfsr(MEC_ACC, addr, asi, 1); return (1); @@ -1887,3 +1895,19 @@ sis_memory_read(addr, data, length) memcpy(data, mem, length); return (length); } + +extern struct pstate sregs; + +void +boot_init () +{ + mec_write(MEC_WCR, 0); /* zero waitstates */ + mec_write(MEC_TRAPD, 0); /* turn off watch-dog */ + mec_write(MEC_RTC_SCALER, sregs.freq-1); /* generate 1 MHz RTC tick */ + mec_write(MEC_MEMCFG, (3 << 18) | (4 << 10)); /* 1 MB ROM, 4 MB RAM */ + sregs.wim = 2; + sregs.psr = 0x110010e0; + sregs.r[30] = RAM_END; + sregs.r[14] = sregs.r[30] - 96*4; + mec_mcr |= 1; /* power-down enabled */ +} diff --git a/sim/erc32/func.c b/sim/erc32/func.c index e6744ee..7034393 100644 --- a/sim/erc32/func.c +++ b/sim/erc32/func.c @@ -468,6 +468,7 @@ exec_cmd(sregs, cmd) } sregs->pc = len & ~3; sregs->npc = sregs->pc + 4; + if ((sregs->pc != 0) && (ebase.simtime == 0)) boot_init(); printf("resuming at 0x%08x\n",sregs->pc); if ((cmd2 = strtok(NULL, " \t\n\r")) != NULL) { stat = run_sim(sregs, VAL(cmd2), 0); diff --git a/sim/erc32/interf.c b/sim/erc32/interf.c index 63b3f38..9ac455f 100644 --- a/sim/erc32/interf.c +++ b/sim/erc32/interf.c @@ -78,6 +78,7 @@ run_sim(sregs, icount, dis) init_stdio(); sregs->starttime = time(NULL); irq = 0; + if ((sregs->pc != 0) && (ebase.simtime == 0)) boot_init(); while (!sregs->err_mode & (icount > 0)) { sregs->fhold = 0;