From patchwork Thu Dec 11 11:15:15 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yao Qi X-Patchwork-Id: 4173 Received: (qmail 2310 invoked by alias); 11 Dec 2014 11:15:50 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 2286 invoked by uid 89); 11 Dec 2014 11:15:49 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.2 X-HELO: relay1.mentorg.com Received: from relay1.mentorg.com (HELO relay1.mentorg.com) (192.94.38.131) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 11 Dec 2014 11:15:47 +0000 Received: from svr-orw-fem-05.mgc.mentorg.com ([147.34.97.43]) by relay1.mentorg.com with esmtp id 1Xz1ii-0005kQ-Gs from Yao_Qi@mentor.com for gdb-patches@sourceware.org; Thu, 11 Dec 2014 03:15:44 -0800 Received: from qiyao.dyndns.org.com (147.34.91.1) by svr-orw-fem-05.mgc.mentorg.com (147.34.97.43) with Microsoft SMTP Server id 14.3.181.6; Thu, 11 Dec 2014 03:15:44 -0800 From: Yao Qi To: Subject: [PATCH] Detect 64-bit-ness in PowerPC Book III-E Date: Thu, 11 Dec 2014 19:15:15 +0800 Message-ID: <1418296515-8689-1-git-send-email-yao@codesourcery.com> MIME-Version: 1.0 X-IsSubscribed: yes This patch is to teach GDBServer to detect 64-bit inferior correctly. We find a problem that GDBServer is unable to detect on an e5500 core processor. Current GDBServer assumes that MSR is a 64-bit register, but MSR is a 32-bit register in Book III-E. This patch is to fix this problem by checking both bits in MSR, in order to handle both Book III-S and Book III-E. Is it OK? gdb/gdbserver: 2014-12-11 Yao Qi * linux-ppc-low.c (ppc_arch_setup) [__powerpc64__]: Change variable msr to type 'unsigned long'. Check bit 63 or bit 31 is one. --- gdb/gdbserver/linux-ppc-low.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/gdb/gdbserver/linux-ppc-low.c b/gdb/gdbserver/linux-ppc-low.c index 8fd4b38..0c0ced6 100644 --- a/gdb/gdbserver/linux-ppc-low.c +++ b/gdb/gdbserver/linux-ppc-low.c @@ -401,7 +401,7 @@ ppc_arch_setup (void) { const struct target_desc *tdesc; #ifdef __powerpc64__ - long msr; + unsigned long msr; struct regcache *regcache; /* On a 64-bit host, assume 64-bit inferior process with no @@ -411,13 +411,17 @@ ppc_arch_setup (void) current_process ()->tdesc = tdesc; ppc_hwcap = 0; - /* Only if the high bit of the MSR is set, we actually have - a 64-bit inferior. */ + /* We actually have a 64-bit inferior only if the certain bit of the + MSR is set. The PowerISA Book III-S MSR is different from the + PowerISA Book III-E MSR. The Book III-S MSR is 64 bits wide, and + its MSR[SF] is the bit 0 of a 64-bit value. Book III-E MSR is 32 + bits wide, and its MSR[CM] is the bit 0 of a 32-bit value. We check + both here. */ regcache = new_register_cache (tdesc); fetch_inferior_registers (regcache, find_regno (tdesc, "msr")); collect_register_by_name (regcache, "msr", &msr); free_register_cache (regcache); - if (msr < 0) + if (msr & 0x8000000080000000) { ppc_get_hwcap (&ppc_hwcap); if (ppc_hwcap & PPC_FEATURE_CELL)