From patchwork Sat Oct 25 02:05:54 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yao Qi X-Patchwork-Id: 3369 Received: (qmail 17228 invoked by alias); 25 Oct 2014 02:10:58 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 17203 invoked by uid 89); 25 Oct 2014 02:10:52 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.2 X-HELO: relay1.mentorg.com Received: from relay1.mentorg.com (HELO relay1.mentorg.com) (192.94.38.131) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sat, 25 Oct 2014 02:10:49 +0000 Received: from svr-orw-fem-05.mgc.mentorg.com ([147.34.97.43]) by relay1.mentorg.com with esmtp id 1XhqoY-0005vo-91 from Yao_Qi@mentor.com for gdb-patches@sourceware.org; Fri, 24 Oct 2014 19:10:46 -0700 Received: from qiyao.dyndns.org.com (147.34.91.1) by svr-orw-fem-05.mgc.mentorg.com (147.34.97.43) with Microsoft SMTP Server id 14.3.181.6; Fri, 24 Oct 2014 19:10:45 -0700 From: Yao Qi To: Subject: [PATCH] Fix skipping stack protector on arm Date: Sat, 25 Oct 2014 10:05:54 +0800 Message-ID: <1414202754-8398-1-git-send-email-yao@codesourcery.com> MIME-Version: 1.0 X-IsSubscribed: yes This patch fixes the bug in my patch skipping stack protector https://www.sourceware.org/ml/gdb-patches/2010-12/msg00110.html In my skipping stack protector patch, I misunderstood the constant vs. immediate on instruction encodings, and treated immediate as constant by mistake. The instruction 'ldr Rd, [PC, #immed]' loads the address of __stack_chk_guard to Rd, and #immed is an offset from PC. We should get the __stack_chk_guard from *(pc + #immed). As a result of this mistake, arm_analyze_load_stack_chk_guard returns the wrong address of __stack_chk_guard, and the symbol __stack_chk_guard can't be found. However, we continue to match the following instructions when symbol isn't found, so the code still works. In other words, the code just matches the instruction pattern without checking __stack_chk_guard symbol correctly. Joel's patch makes the heuristics stricter that we stop matching instructions if symbol __stack_chk_guard isn't found. Then the bug is exposed. This patch is to correct the load address computation for ldr instruction, and it fixes some fails in gdb.mi/gdb792.exp on armv4t both arm and thumb mode. Regression tested on arm-linux-gnueabi target with {armv4t, armv7-a} x {marm, mthumb} x {-fstack-protector,-fno-stack-protector} gdb: 2014-10-25 Yao Qi * arm-tdep.c (arm_analyze_load_stack_chk_guard): Compute the loaded address correctly of ldr instruction. --- gdb/arm-tdep.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 5dccf0a..5e3c6c9 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -1204,7 +1204,9 @@ arm_analyze_load_stack_chk_guard(CORE_ADDR pc, struct gdbarch *gdbarch, { *destreg = bits (insn1, 8, 10); *offset = 2; - address = bits (insn1, 0, 7); + address = (pc & 0xfffffffc) + 4 + (bits (insn1, 0, 7) << 2); + address = read_memory_unsigned_integer (address, 4, + byte_order_for_code); } else if ((insn1 & 0xfbf0) == 0xf240) /* movw Rd, #const */ { @@ -1233,9 +1235,12 @@ arm_analyze_load_stack_chk_guard(CORE_ADDR pc, struct gdbarch *gdbarch, unsigned int insn = read_memory_unsigned_integer (pc, 4, byte_order_for_code); - if ((insn & 0x0e5f0000) == 0x041f0000) /* ldr Rd, #immed */ + if ((insn & 0x0e5f0000) == 0x041f0000) /* ldr Rd, [PC, #immed] */ { - address = bits (insn, 0, 11); + address = bits (insn, 0, 11) + pc + 8; + address = read_memory_unsigned_integer (address, 4, + byte_order_for_code); + *destreg = bits (insn, 12, 15); *offset = 4; }