From patchwork Wed Aug 13 13:12:14 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Omair Javaid X-Patchwork-Id: 2388 Received: (qmail 25256 invoked by alias); 13 Aug 2014 13:13:44 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 25179 invoked by uid 89); 13 Aug 2014 13:13:43 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-we0-f180.google.com Received: from mail-we0-f180.google.com (HELO mail-we0-f180.google.com) (74.125.82.180) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Wed, 13 Aug 2014 13:13:42 +0000 Received: by mail-we0-f180.google.com with SMTP id w61so11267035wes.39 for ; Wed, 13 Aug 2014 06:13:39 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=oTXUFykSYMUWh8SBKkqEacaG9iNHD5IOf3Z3TaB4J2g=; b=Q7wz6BQvjT4fT1nu3rAnHZuOdT42SvRb/RPY8c9R4swGH3uxSHybIQ93uJ6Ei5FwQo Grur83JRsPaSrXRmuZVOVkPxF7rOugOT/26Kbf7sb/x505EMXAaYBN52Lgd0GXArqSuO 76dVdrBu7X1EEM4pGIUmLW/dk+M/T9G8hzgZqncATP+wXFyvwv4+Gz1pPwKx5D7HbWJz Xt8ZhKyvFdz7rh8JCOltUe20ucdpAw7DfeLaQjU+l8KkddmZnLWSxksiO8Up+BkmfcVX wGrZiCr88tnB6E6zuYdo9Z3UUokK66P8xxnYA/DRKWZIaJmeqbiQZIjLWo7DSRiRjrjQ Q58g== X-Gm-Message-State: ALoCoQkfShKO0jtCJlg36Ru24Zl4dPungtV8YN9GOkiWKlFDV7vNxJS4L5GF9WR/9dKCeTA8VtOy X-Received: by 10.180.12.239 with SMTP id b15mr38158244wic.75.1407935619138; Wed, 13 Aug 2014 06:13:39 -0700 (PDT) Received: from localhost.localdomain ([182.185.185.192]) by mx.google.com with ESMTPSA id w14sm50806711wij.2.2014.08.13.06.13.37 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 13 Aug 2014 06:13:38 -0700 (PDT) From: Omair Javaid To: gdb-patches@sourceware.org Cc: patches@linaro.org Subject: [PATCH v3 5/6] Implement support for recording vector data transfer instructions Date: Wed, 13 Aug 2014 18:12:14 +0500 Message-Id: <1407935535-27978-6-git-send-email-omair.javaid@linaro.org> In-Reply-To: <1407935535-27978-1-git-send-email-omair.javaid@linaro.org> References: <1407935535-27978-1-git-send-email-omair.javaid@linaro.org> X-IsSubscribed: yes gdb: 2014-08-13 Omair Javaid * arm-tdep.c (arm_record_vdata_transfer_insn): Added record handler for vector data transfer instructions. (arm_record_coproc_data_proc): Updated. --- gdb/arm-tdep.c | 98 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 97 insertions(+), 1 deletion(-) diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 315b5b0..7f651bc 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -11990,6 +11990,102 @@ arm_record_unsupported_insn (insn_decode_record *arm_insn_r) return -1; } +/* Record handler for vector data transfer instructions. */ + +static int +arm_record_vdata_transfer_insn (insn_decode_record *arm_insn_r) +{ + uint32_t bits_a, bit_c, bit_l, reg_t, reg_v; + uint32_t record_buf[4]; + + const int num_regs = gdbarch_num_regs (arm_insn_r->gdbarch); + reg_t = bits (arm_insn_r->arm_insn, 12, 15); + reg_v = bits (arm_insn_r->arm_insn, 21, 23); + bits_a = bits (arm_insn_r->arm_insn, 21, 23); + bit_l = bit (arm_insn_r->arm_insn, 20); + bit_c = bit (arm_insn_r->arm_insn, 8); + + /* Handle VMOV instruction. */ + if (bit_l && bit_c) + { + record_buf[0] = reg_t; + arm_insn_r->reg_rec_count = 1; + } + else if (bit_l && !bit_c) + { + /* Handle VMOV instruction. */ + if (bits_a == 0x00) + { + if (bit (arm_insn_r->arm_insn, 20)) + record_buf[0] = reg_t; + else + record_buf[0] = num_regs + (bit (arm_insn_r->arm_insn, 7) | + (reg_v << 1)); + + arm_insn_r->reg_rec_count = 1; + } + /* Handle VMRS instruction. */ + else if (bits_a == 0x07) + { + if (reg_t == 15) + reg_t = ARM_PS_REGNUM; + + record_buf[0] = reg_t; + arm_insn_r->reg_rec_count = 1; + } + } + else if (!bit_l && !bit_c) + { + /* Handle VMOV instruction. */ + if (bits_a == 0x00) + { + if (bit (arm_insn_r->arm_insn, 20)) + record_buf[0] = reg_t; + else + record_buf[0] = num_regs + (bit (arm_insn_r->arm_insn, 7) | + (reg_v << 1)); + + arm_insn_r->reg_rec_count = 1; + } + /* Handle VMSR instruction. */ + else if (bits_a == 0x07) + { + record_buf[0] = ARM_FPSCR_REGNUM; + arm_insn_r->reg_rec_count = 1; + } + } + else if (!bit_l && bit_c) + { + /* Handle VMOV instruction. */ + if (!(bits_a & 0x04)) + { + record_buf[0] = (reg_v | (bit (arm_insn_r->arm_insn, 7) << 4)) + + ARM_D0_REGNUM; + arm_insn_r->reg_rec_count = 1; + } + /* Handle VDUP instruction. */ + else + { + if (bit (arm_insn_r->arm_insn, 21)) + { + reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4); + record_buf[0] = reg_v + ARM_D0_REGNUM; + record_buf[1] = reg_v + ARM_D0_REGNUM + 1; + arm_insn_r->reg_rec_count = 2; + } + else + { + reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4); + record_buf[0] = reg_v + ARM_D0_REGNUM; + arm_insn_r->reg_rec_count = 1; + } + } + } + + REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); + return 0; +} + /* Record handler for extension register load/store instructions. */ static int @@ -12467,7 +12563,7 @@ arm_record_coproc_data_proc (insn_decode_record *arm_insn_r) /* Advanced SIMD, VFP instructions. */ if (!op1_sbit && op) - return arm_record_unsupported_insn (arm_insn_r); + return arm_record_vdata_transfer_insn (arm_insn_r); } else {