diff mbox

[5/5] : Enhancements to "flags": add cpsr_flags to aarch64

Message ID 001a1137efd0d18af3052cf0df46@google.com
State New, archived
Headers

Commit Message

Doug Evans Feb. 29, 2016, 11:19 p.m. UTC 
  Hi.

This patch adds a definition for aarch64's cpsr.
This register has a two-bit bitfield: EL (which is what started all of  
this).
I didn't do arm32 because I don't have at immediate hand the spec.

2016-02-29  Doug Evans  <dje@google.com>

	* features/aarch64-core.xml (cpsr_flags): New flags type.
	(cpsr): Use it.
	* features/aarch64.c: Regenerate.
diff mbox

Patch

diff --git a/gdb/features/aarch64-core.xml b/gdb/features/aarch64-core.xml
index b5944fc..8f96296 100644
--- a/gdb/features/aarch64-core.xml
+++ b/gdb/features/aarch64-core.xml
@@ -42,5 +42,26 @@ 
    <reg name="sp" bitsize="64" type="data_ptr"/>

    <reg name="pc" bitsize="64" type="code_ptr"/>
-  <reg name="cpsr" bitsize="32"/>
+
+  <flags id="cpsr_flags" size="4">
+    <field name="SP" start="0" type="bool"/>
+    <field name="" start="1" end="1"/>
+    <field name="EL" start="2" end="3"/>
+    <field name="nRW" start="4" type="bool"/>
+    <field name="" start="5" end="5"/>
+    <field name="F" start="6" type="bool"/>
+    <field name="I" start="7" type="bool"/>
+    <field name="A" start="8" type="bool"/>
+    <field name="D" start="9" type="bool"/>
+
+    <field name="IL" start="20" type="bool"/>
+    <field name="SS" start="21" type="bool"/>
+
+    <field name="V" start="28" type="bool"/>
+    <field name="C" start="29" type="bool"/>
+    <field name="Z" start="30" type="bool"/>
+    <field name="N" start="31" type="bool"/>
+  </flags>
+  <reg name="cpsr" bitsize="32" type="cpsr_flags"/>
+
  </feature>
diff --git a/gdb/features/aarch64.c b/gdb/features/aarch64.c
index 1e9a99d..cec6956 100644
--- a/gdb/features/aarch64.c
+++ b/gdb/features/aarch64.c
@@ -17,6 +17,23 @@  initialize_tdesc_aarch64 (void)
    set_tdesc_architecture (result, bfd_scan_arch ("aarch64"));

    feature = tdesc_create_feature (result, "org.gnu.gdb.aarch64.core");
+  type = tdesc_create_flags (feature, "cpsr_flags", 4);
+  tdesc_add_flag (type, 0, "SP");
+  tdesc_add_bitfield (type, "", 1, 1);
+  tdesc_add_bitfield (type, "EL", 2, 3);
+  tdesc_add_flag (type, 4, "nRW");
+  tdesc_add_bitfield (type, "", 5, 5);
+  tdesc_add_flag (type, 6, "F");
+  tdesc_add_flag (type, 7, "I");
+  tdesc_add_flag (type, 8, "A");
+  tdesc_add_flag (type, 9, "D");
+  tdesc_add_flag (type, 20, "IL");
+  tdesc_add_flag (type, 21, "SS");
+  tdesc_add_flag (type, 28, "V");
+  tdesc_add_flag (type, 29, "C");
+  tdesc_add_flag (type, 30, "Z");
+  tdesc_add_flag (type, 31, "N");
+
    tdesc_create_reg (feature, "x0", 0, 1, NULL, 64, "int");
    tdesc_create_reg (feature, "x1", 1, 1, NULL, 64, "int");
    tdesc_create_reg (feature, "x2", 2, 1, NULL, 64, "int");
@@ -50,7 +67,7 @@  initialize_tdesc_aarch64 (void)
    tdesc_create_reg (feature, "x30", 30, 1, NULL, 64, "int");
    tdesc_create_reg (feature, "sp", 31, 1, NULL, 64, "data_ptr");
    tdesc_create_reg (feature, "pc", 32, 1, NULL, 64, "code_ptr");
-  tdesc_create_reg (feature, "cpsr", 33, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "cpsr", 33, 1, NULL, 32, "cpsr_flags");

    feature = tdesc_create_feature (result, "org.gnu.gdb.aarch64.fpu");
    field_type = tdesc_named_type (feature, "ieee_double");