mbox series

[v4,0/2] sim: riscv: Compressed instruction simulation

Message ID 20231221111139.26341-1-jaydeep.patil@imgtec.com
Headers
Series sim: riscv: Compressed instruction simulation |

Message

Jaydeep Patil Dec. 21, 2023, 11:11 a.m. UTC 
  From: Jaydeep Patil <jaydeep.patil@imgtec.com>

Hi Mike, Andrew,

Addressed review comments.
 - Fixed riscv opcodes for NULL match_func
 - Added models for C extension
 - Using RA and SP from sim_riscv_regnum

I have removed the support for semi-hosting from this patch series, will push it
later once the spec is clear.

Jaydeep Patil (2):
  [sim/riscv] Fix crash during instruction decoding
  [sim/riscv] Add support for compressed integer instructions

 opcodes/riscv-dis.c             |   2 +-
 sim/riscv/model_list.def        |   9 +
 sim/riscv/sim-main.c            | 338 ++++++++++++++++++++++++++++++--
 sim/testsuite/riscv/allinsn.exp |  19 ++
 sim/testsuite/riscv/c-ext.s     | 110 +++++++++++
 5 files changed, 466 insertions(+), 12 deletions(-)
 create mode 100644 sim/testsuite/riscv/c-ext.s