From patchwork Tue Nov 1 15:11:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Frysinger X-Patchwork-Id: 55256 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 970EC3857413 for ; Tue, 1 Nov 2022 16:26:49 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 970EC3857413 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1667320009; bh=l5Z722DKVwJTBibq/DM5luWUzfy7wUuX5f3WBYzmcYk=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=n0MhT0J7qSYAOOtkzVHmqEWLwcb5ylyLP92km7oBvS7p9Q9GxtpOqgiN3IhXq3tQu DutgO2lMwdrG79YsEEmBIq+lbsOtAPhN/G3ZKK6mUmChzeTQAy9DnybT7PmhvGtoUZ LvTfvE5H5YYvqW5yt89cKPlDy90KQSBWwuCoMhKE= X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from smtp.gentoo.org (woodpecker.gentoo.org [IPv6:2001:470:ea4a:1:5054:ff:fec7:86e4]) by sourceware.org (Postfix) with ESMTP id 014CE3858D35 for ; Tue, 1 Nov 2022 16:26:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 014CE3858D35 Received: by smtp.gentoo.org (Postfix, from userid 559) id D487B340DA4; Tue, 1 Nov 2022 16:26:21 +0000 (UTC) To: gdb-patches@sourceware.org Subject: [PATCH 00/27] sim: sim_cpu: invert sim_cpu storage Date: Tue, 1 Nov 2022 20:56:31 +0545 Message-Id: <20221101151158.24916-1-vapier@gentoo.org> X-Mailer: git-send-email 2.37.3 MIME-Version: 1.0 X-Spam-Status: No, score=-5.1 required=5.0 tests=BAYES_00, JMQ_SPF_NEUTRAL, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Mike Frysinger via Gdb-patches From: Mike Frysinger Reply-To: Mike Frysinger Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org Sender: "Gdb-patches" This is similar to the patch series for inverting sim_state storage: https://sourceware.org/pipermail/gdb-patches/2021-May/178806.html There's more patches here than that series because every arch defines a custom sim_cpu with real content. Basically we: 1) rename the per-arch "sim_cpu" type to "$arch_sim_cpu", 2) rename the common "sim_cpu_base" to "sim_cpu", 3) add a new "arch_data" to the new common "sim_cpu", 4) define $ARCH_SIM_CPU macro to turn common sim_cpu into the $arch_sim_cpu data. This is another required step along the way to creating a single sim with multiple arch backends in it -- we can't have common data structs (like "sim_cpu" which is used everywhere) having completely different layouts & contents between archs. Mike Frysinger (27): sim: sim_cpu: invert sim_cpu storage sim: bfin: invert sim_cpu storage sim: ft32: invert sim_cpu storage sim: msp430: invert sim_cpu storage sim: moxie: invert sim_cpu storage sim: avr: invert sim_cpu storage sim: microblaze: invert sim_cpu storage sim: aarch64: invert sim_cpu storage sim: mcore: invert sim_cpu storage sim: v850: invert sim_cpu storage sim: mips: invert sim_cpu storage sim: m68hc11: invert sim_cpu storage sim: h8300: switch to cpu for state sim: h8300: invert sim_cpu storage sim: example-synacor: invert sim_cpu storage sim: pru: invert sim_cpu storage sim: riscv: invert sim_cpu storage sim: cgen: prep for inverting sim_cpu storage sim: bpf: invert sim_cpu storage sim: cris: invert sim_cpu storage sim: frv: invert sim_cpu storage sim: iq2000: invert sim_cpu storage sim: lm32: invert sim_cpu storage sim: m32r: invert sim_cpu storage sim: or1k: invert sim_cpu storage sim: enable common sim_cpu usage everywhere sim: fully merge sim_cpu_base into sim_cpu sim/aarch64/cpustate.c | 242 +++++++----- sim/aarch64/cpustate.h | 2 +- sim/aarch64/interp.c | 3 +- sim/aarch64/sim-main.h | 6 +- sim/aarch64/simulator.c | 5 +- sim/arm/sim-main.h | 5 - sim/avr/interp.c | 201 +++++----- sim/avr/sim-main.h | 6 +- sim/bfin/interp.c | 5 +- sim/bfin/sim-main.h | 8 +- sim/bpf/cpu.h | 2 +- sim/bpf/sim-main.h | 7 +- sim/common/cgen-cpu.h | 5 + sim/common/sim-cpu.c | 18 +- sim/common/sim-cpu.h | 61 +-- sim/cr16/sim-main.h | 5 - sim/cris/cpuv10.h | 2 +- sim/cris/cpuv32.h | 2 +- sim/cris/cris-tmpl.c | 19 +- sim/cris/sim-if.c | 28 +- sim/cris/sim-main.h | 15 +- sim/cris/traps.c | 412 +++++++++---------- sim/d10v/sim-main.h | 5 - sim/example-synacor/interp.c | 3 +- sim/example-synacor/sim-main.c | 72 ++-- sim/example-synacor/sim-main.h | 7 +- sim/frv/cpu.h | 2 +- sim/frv/sim-main.h | 35 +- sim/ft32/ft32-sim.h | 2 + sim/ft32/interp.c | 181 +++++---- sim/ft32/sim-main.h | 9 - sim/h8300/compile.c | 700 ++++++++++++++------------------- sim/h8300/sim-main.h | 9 +- sim/iq2000/cpu.h | 2 +- sim/iq2000/sim-main.h | 11 +- sim/lm32/cpu.h | 2 +- sim/lm32/sim-main.h | 12 +- sim/m32r/cpu.h | 2 +- sim/m32r/cpu2.h | 2 +- sim/m32r/cpux.h | 2 +- sim/m32r/sim-main.h | 13 +- sim/m68hc11/dv-m68hc11.c | 121 +++--- sim/m68hc11/dv-m68hc11eepr.c | 42 +- sim/m68hc11/dv-m68hc11sio.c | 76 ++-- sim/m68hc11/dv-m68hc11spi.c | 45 ++- sim/m68hc11/dv-m68hc11tim.c | 128 +++--- sim/m68hc11/emulos.c | 4 +- sim/m68hc11/interp.c | 59 +-- sim/m68hc11/interrupts.c | 14 +- sim/m68hc11/m68hc11_sim.c | 195 ++++----- sim/m68hc11/sim-main.h | 114 +++--- sim/mcore/interp.c | 59 +-- sim/mcore/sim-main.h | 7 +- sim/microblaze/interp.c | 7 +- sim/microblaze/microblaze.h | 2 +- sim/microblaze/sim-main.h | 5 +- sim/mips/interp.c | 112 +++--- sim/mips/sim-main.h | 49 ++- sim/mn10300/sim-main.h | 11 - sim/moxie/interp.c | 9 +- sim/moxie/sim-main.h | 16 +- sim/msp430/msp430-sim.c | 212 +++++----- sim/msp430/msp430-sim.h | 2 +- sim/msp430/sim-main.h | 10 +- sim/or1k/cpu.h | 2 +- sim/or1k/or1k.c | 36 +- sim/or1k/sim-main.h | 12 +- sim/or1k/traps.c | 18 +- sim/pru/interp.c | 28 +- sim/pru/pru.h | 2 +- sim/pru/sim-main.h | 5 +- sim/riscv/sim-main.c | 439 ++++++++++++--------- sim/riscv/sim-main.h | 5 +- sim/sh/sim-main.h | 5 - sim/v850/interp.c | 15 +- sim/v850/sim-main.h | 22 +- sim/v850/v850.igen | 4 +- 77 files changed, 2068 insertions(+), 1954 deletions(-)