Hi All,
This is a refactoring to allow aarch64_float_const_representable_p
to take an additional mode parameter which is the mode of the constant being
analyzed. This will be required by the next patch in the series.
No functional change is expected from this change.
Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.
Ok for master?
Thanks,
Tamar
gcc/ChangeLog:
* config/aarch64/aarch64-protos.h (aarch64_float_const_representable_p):
Add mode param.
* config/aarch64/aarch64.cc (aarch64_float_const_representable_p):
Add mode param.
(aarch64_print_operand, aarch64_rtx_costs,
aarch64_simd_valid_immediate): Use it.
* config/aarch64/aarch64.md: Likewise.
* config/aarch64/constraints.md: Likewise.
* config/aarch64/predicates.md: Likewise.
---
--
@@ -973,7 +973,7 @@ bool aarch64_mov128_immediate (rtx);
void aarch64_split_simd_move (rtx, rtx);
/* Check for a legitimate floating point constant for FMOV. */
-bool aarch64_float_const_representable_p (rtx);
+bool aarch64_float_const_representable_p (rtx, machine_mode);
extern int aarch64_epilogue_uses (int);
@@ -12317,7 +12317,7 @@ aarch64_print_operand (FILE *f, rtx x, int code)
fputc ('0', f);
break;
}
- else if (aarch64_float_const_representable_p (x))
+ else if (aarch64_float_const_representable_p (x, GET_MODE (x)))
{
#define buf_size 20
char float_buf[buf_size] = {'\0'};
@@ -14233,7 +14233,7 @@ aarch64_rtx_costs (rtx x, machine_mode mode, int outer ATTRIBUTE_UNUSED,
/* First determine number of instructions to do the move
as an integer constant. */
- if (!aarch64_float_const_representable_p (x)
+ if (!aarch64_float_const_representable_p (x, mode)
&& !aarch64_can_const_movi_rtx_p (x, mode)
&& aarch64_float_const_rtx_p (x))
{
@@ -14252,7 +14252,7 @@ aarch64_rtx_costs (rtx x, machine_mode mode, int outer ATTRIBUTE_UNUSED,
if (speed)
{
/* mov[df,sf]_aarch64. */
- if (aarch64_float_const_representable_p (x))
+ if (aarch64_float_const_representable_p (x, mode))
/* FMOV (scalar immediate). */
*cost += extra_cost->fp[mode == DFmode || mode == DDmode].fpconst;
else if (!aarch64_float_const_zero_rtx_p (x))
@@ -23032,7 +23032,7 @@ aarch64_simd_valid_immediate (rtx op, simd_immediate_info *info,
{
rtx elt = CONST_VECTOR_ENCODED_ELT (op, 0);
if (aarch64_float_const_zero_rtx_p (elt)
- || aarch64_float_const_representable_p (elt))
+ || aarch64_float_const_representable_p (elt, elt_mode))
{
if (info)
*info = simd_immediate_info (elt_float_mode, elt);
@@ -25119,10 +25119,10 @@ aarch64_c_mode_for_suffix (char suffix)
'n' is an integer in the range 16 <= n <= 31.
'r' is an integer in the range -3 <= r <= 4. */
-/* Return true iff X can be represented by a quarter-precision
+/* Return true iff X with mode MODE can be represented by a quarter-precision
floating point immediate operand X. Note, we cannot represent 0.0. */
bool
-aarch64_float_const_representable_p (rtx x)
+aarch64_float_const_representable_p (rtx x, machine_mode mode)
{
/* This represents our current view of how many bits
make up the mantissa. */
@@ -25133,11 +25133,12 @@ aarch64_float_const_representable_p (rtx x)
bool fail;
x = unwrap_const_vec_duplicate (x);
+ mode = GET_MODE_INNER (mode);
if (!CONST_DOUBLE_P (x))
return false;
- if (GET_MODE (x) == VOIDmode
- || (GET_MODE (x) == HFmode && !TARGET_FP_F16INST))
+ if (mode == VOIDmode
+ || (mode == HFmode && !TARGET_FP_F16INST))
return false;
r = *CONST_DOUBLE_REAL_VALUE (x);
@@ -25150,7 +25151,7 @@ aarch64_float_const_representable_p (rtx x)
return false;
/* For BFmode, only handle 0.0. */
- if (GET_MODE (x) == BFmode)
+ if (mode == BFmode)
return real_iszero (&r, false);
/* Extract exponent. */
@@ -1712,7 +1712,7 @@ (define_split
(match_operand:GPF_HF 1 "const_double_operand"))]
"can_create_pseudo_p ()
&& !aarch64_can_const_movi_rtx_p (operands[1], <MODE>mode)
- && !aarch64_float_const_representable_p (operands[1])
+ && !aarch64_float_const_representable_p (operands[1], <MODE>mode)
&& !aarch64_float_const_zero_rtx_p (operands[1])
&& aarch64_float_const_rtx_p (operands[1])"
[(const_int 0)]
@@ -447,7 +447,7 @@ (define_constraint "Ufc"
"A floating point constant which can be used with an\
FMOV immediate operation."
(and (match_code "const_double,const_vector")
- (match_test "aarch64_float_const_representable_p (op)")))
+ (match_test "aarch64_float_const_representable_p (op, mode)")))
(define_constraint "Uum"
"A constant that can be used with the U[MIN/MAX] CSSC instructions."
@@ -888,7 +888,7 @@ (define_predicate "aarch64_sve_vsm_immediate"
(define_predicate "aarch64_sve_dup_immediate"
(and (match_code "const,const_vector")
(ior (match_test "aarch64_sve_dup_immediate_p (op)")
- (match_test "aarch64_float_const_representable_p (op)"))))
+ (match_test "aarch64_float_const_representable_p (op, mode)"))))
(define_predicate "aarch64_sve_cmp_vsc_immediate"
(and (match_code "const_int,const_vector")