From patchwork Fri Oct 15 07:51:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tamar Christina X-Patchwork-Id: 46261 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E32533857C75 for ; Fri, 15 Oct 2021 07:52:43 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E32533857C75 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1634284363; bh=BG+fO+2kBHjLvpnGuzKRgy1kd2qwZVhewIpzr5h5ux4=; h=Date:To:Subject:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=XklIwBxFb+Zl1bl47qdhrLq1CamBk8T0bMNvXY8O2nLj5lj4nQKtBAkKHkZ3z2GWc y1riGK0Y5EH+lv4lSmExtNt20OXwCMpLXbvLP2698SpVAfxGcUf9v7yXGmaPj5TQXn ZVxQ851lRJTm4HD2lHPJGZmERFiEobENjmI50b1E= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from EUR04-VI1-obe.outbound.protection.outlook.com (mail-eopbgr80050.outbound.protection.outlook.com [40.107.8.50]) by sourceware.org (Postfix) with ESMTPS id 0B5953857C7F for ; Fri, 15 Oct 2021 07:52:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 0B5953857C7F Received: from DB7PR05CA0069.eurprd05.prod.outlook.com (2603:10a6:10:2e::46) by AM9PR08MB6833.eurprd08.prod.outlook.com (2603:10a6:20b:30b::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4608.15; Fri, 15 Oct 2021 07:52:04 +0000 Received: from DB5EUR03FT023.eop-EUR03.prod.protection.outlook.com (2603:10a6:10:2e:cafe::ed) by DB7PR05CA0069.outlook.office365.com (2603:10a6:10:2e::46) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4608.15 via Frontend Transport; Fri, 15 Oct 2021 07:52:04 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; gcc.gnu.org; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;gcc.gnu.org; dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by DB5EUR03FT023.mail.protection.outlook.com (10.152.20.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4608.15 via Frontend Transport; Fri, 15 Oct 2021 07:52:04 +0000 Received: ("Tessian outbound b9598e0ead92:v103"); Fri, 15 Oct 2021 07:52:04 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: 89ef8f294a3c0433 X-CR-MTA-TID: 64aa7808 Received: from 98d406f98f56.2 by 64aa7808-outbound-1.mta.getcheckrecipient.com id FE8E4AF8-7663-40DB-83EC-7B24AC874788.1; Fri, 15 Oct 2021 07:51:57 +0000 Received: from EUR05-VI1-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id 98d406f98f56.2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Fri, 15 Oct 2021 07:51:57 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=C4fnkT0grcWuLpYoUr5kICScDlmSTMuS7jGRiaSNVQGRjYm4IKS+c/eMJcfX21DXUONJnUyAK+cvXbGYWhu5ZmhkpCgRS010M8RCVJ6LUlbxVXiW3Rp6DAb61xwdb6YL58I8MFy41fEVn68AJ0aqAnL348Ic5g6KPFD8yEP0hj0kLogQXTI0pRJHvIjwOhbdJgXtQW1khj70PyU04D+98QyWndwFNsn0qUH74weyuNC5VouBrwQc9I7nVJdyTQbf26vtNEYNeCQM2yDE61dw3cfTLIZu2jzAxIkDTzeJ00foxCbgToPN9JqrdEpvNLywtzWEkMxQn0tn0FmKUQw0zQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=BG+fO+2kBHjLvpnGuzKRgy1kd2qwZVhewIpzr5h5ux4=; b=OJrFMdYw7HtXFB/LkympEgz7MgwNt0AbnC4ne8bvOC8JTBv8SYxvuRTK00jPdeCoWSTaW1jeGtmk9LnLnO8l8Xmf5bqMdoqZrOgwKAWM31CJprFy6VedvfZemFetd4jyBrzw/JCXSBK4Ilnn19j/Gb47CJJgcVS/9IQb9QY45RqypODVYtiUtwOnkoVZdkgTmG/31H1eAYrSd6hnsi7gpoSHTyAlnn/ai7PyyqdnAGmsDb9vk/sEOtAVygVikaGq1JM5g8wSbe32jzIHSzn7wsLpL+aDagDPRSRZkukCjvhr5whiE/fNb7j2p43Zl0rsJIGgINmI4ZVbV+Tx3RZVhg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none Authentication-Results-Original: gcc.gnu.org; dkim=none (message not signed) header.d=none;gcc.gnu.org; dmarc=none action=none header.from=arm.com; Received: from VI1PR08MB5325.eurprd08.prod.outlook.com (2603:10a6:803:13e::17) by VI1PR0801MB1678.eurprd08.prod.outlook.com (2603:10a6:800:51::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4587.24; Fri, 15 Oct 2021 07:51:44 +0000 Received: from VI1PR08MB5325.eurprd08.prod.outlook.com ([fe80::bd45:5ad5:f666:272a]) by VI1PR08MB5325.eurprd08.prod.outlook.com ([fe80::bd45:5ad5:f666:272a%4]) with mapi id 15.20.4608.016; Fri, 15 Oct 2021 07:51:44 +0000 Date: Fri, 15 Oct 2021 08:51:41 +0100 To: gcc-patches@gcc.gnu.org Subject: [PATCH]AArch64 Lower intrinsics shift to GIMPLE when possible. Message-ID: Content-Disposition: inline User-Agent: Mutt/1.9.4 (2018-02-28) X-ClientProxiedBy: LO4P123CA0293.GBRP123.PROD.OUTLOOK.COM (2603:10a6:600:196::10) To VI1PR08MB5325.eurprd08.prod.outlook.com (2603:10a6:803:13e::17) MIME-Version: 1.0 Received: from arm.com (217.140.106.55) by LO4P123CA0293.GBRP123.PROD.OUTLOOK.COM (2603:10a6:600:196::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4608.14 via Frontend Transport; Fri, 15 Oct 2021 07:51:44 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ea721cd2-ae21-4791-7693-08d98fb0add5 X-MS-TrafficTypeDiagnostic: VI1PR0801MB1678:|AM9PR08MB6833: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true NoDisclaimer: true X-MS-Oob-TLC-OOBClassifiers: OLM:8882;OLM:8882; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: nFoCaV6W2tsAI8htbIR1lnN9pJDU0ere0+x+CJ8E2HXSRDw06i5aPrrBjFhJadHXB+C1QlW4CLkTYgnUmiifaqVXzsDoIEexq27lhuNHjRIkxzC5nU0ihSHqzS94SUv187g0+W2Jhk9v3dEhjmeC6Pz+YHBVtUaKoGI/ns4+66tqc+jECxfZyU39SHUeMGGybdWu5G4DLDGVx5PtS2ILtIx0M1xzt/z9uAnaYxRUignojPIWNxfIJEtwcQmg5zxYegz+U1Oq+ks3VtDYBTRSVc+irvM05OfKcH87CPvmkWqPznU3LiC2EidYzOYGSxazkkbEgYt5yD5BIlq26lTLMC4oGiHmWHsrwmu5KLErdh5Iw5RR9QTf13JQXBhdo3pZAF4NG0qUMLt94zo4TjQLPpcj4FtSlO6jI9ydVXiOhM3E+xujcazCPWte9xR4n1XhKbRaAQr1HLMF+tH7K9guayw0s6hySawspgHvhqf1pO5PF/Ah+YND+H8TzbakLLWm3sXCX5Rz/j46m6gTDL+Za4Rw8y437AiqqagbHEcvBIZRqoptlaRZwaH8Bh1Q2ZbhYQyEETO7Lbi6pKaB5wZUIq9WtZu0BqhEB5xRsoL7f0XOsl7J6PZ4jgexAg3L+4rhx1sAKKCe2umBtPTqNwut/H4l8+4QRaNrOcnA3iiQyvCemFUoxAJ+mCwymNcF8KBBqEK7hpGUVrXqqhHn4npyY3edfbug1Nj9CoMRq5XRmGGKayi+/CH5aGI7tBJXQ1M+jtRS6b3G4GHuFpfaf7pFiv2Y9s1T2IfECaua8GgJ2l9qa0H7vQKxscfWgCnwiRv8x2226fJLn1sXL50ggSNFAw== X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:VI1PR08MB5325.eurprd08.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(366004)(5660300002)(316002)(8676002)(44832011)(6666004)(8886007)(508600001)(86362001)(956004)(2616005)(38100700002)(38350700002)(4326008)(8936002)(33964004)(44144004)(26005)(7696005)(52116002)(2906002)(186003)(55016002)(235185007)(66556008)(66946007)(36756003)(6916009)(66476007)(4216001)(2700100001); DIR:OUT; SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0801MB1678 Original-Authentication-Results: gcc.gnu.org; dkim=none (message not signed) header.d=none;gcc.gnu.org; dmarc=none action=none header.from=arm.com; X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DB5EUR03FT023.eop-EUR03.prod.protection.outlook.com X-MS-Office365-Filtering-Correlation-Id-Prvs: 66f8c40a-b016-4853-ab3b-08d98fb0a1e0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: W54OW1M6dhERL/8c2ROjCQDAt/0GcyXxa4PogOHVZNNRLPm+S1YUXjfIIND9FvROEX066WqGgut9BLzgs3ub2M6YNCEn+XqdobPfWwCKI6fna/4CyW/iWv3GvJ/4XjdV9QGm4Tsfwi3WJq8zSMLei7ifa5lYjCgZCiQNQRE1evmuq0UzIyp/MAbYWtibUBskO7Hmaf4sEeYPE5N4HPi6EYbOf7s4f5EV5+gH8zg8Y7ulUX4P6qfOU4xLovX79yVTH6Tl+VqTq7k7DF3rVEpizuj/TujWJVI39ykP1UgPdzRQB2x+NO0g3I748hsVvDDZpFU0/bExQPOVC/hpuq48JEeF3T8/E32FkqMx4jy9zU4UgttC7pOPbkHMAcCUMD0ePFgtz6ecxzx6DUlJG9Bis4aD4FLFzEfpcdwFP1c6IMGo0qfBkxpr6y/CS+enw09KP6meaVq5U46D2JsWzmmaRPCGj33HRdmKqbAR0/wfHgdkV5t0iiLlRs4Nw+IykByYr9R/gobczRN873sp/xtAMZBYbUr101644q/ZOj3KgPqqh8i8fsC3DgkzAUV9b2J7qpht/aX7PsCtltrtUInyh2BYkPPQ9H5Gti/K5VQIbdn8zfm+40bE8fuErScgkBDclo6EMzB1JpyVJAlL2xjBYIQtxK9LFayzkCmkq6L7fC7riGppLbiSW3JsN4SxMEBE+Yn85vEhw+ijiZe+2NIghxFqoZ9JTR405ZD2hQdU+EI9BDi3vBT5sXo2dsL+A1FQPTdj7Ak45wJcGwbyliNWXaPE/Dk0qHSV5EqoactyEM8s6DYeFFwZxQO51x3AWOO+oJ5ozTCcW2jipNf1UlPjqg== X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(86362001)(81166007)(26005)(356005)(47076005)(82310400003)(2616005)(235185007)(336012)(36756003)(956004)(8676002)(6666004)(36860700001)(8936002)(2906002)(55016002)(7696005)(316002)(4326008)(70586007)(8886007)(44144004)(508600001)(5660300002)(44832011)(6916009)(70206006)(186003)(33964004)(4216001)(2700100001); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Oct 2021 07:52:04.2945 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ea721cd2-ae21-4791-7693-08d98fb0add5 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT023.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR08MB6833 X-Spam-Status: No, score=-13.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_LOTSOFHASH, KAM_SHORT, MSGID_FROM_MTA_HEADER, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tamar Christina via Gcc-patches From: Tamar Christina Reply-To: Tamar Christina Cc: Richard.Earnshaw@arm.com, nd@arm.com, richard.sandiford@arm.com, Marcus.Shawcroft@arm.com Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Hi All, This lowers shifts to GIMPLE when the C interpretations of the shift operations matches that of AArch64. In C shifting right by BITSIZE is undefined, but the behavior is defined in AArch64. Additionally negative shifts lefts are undefined in C but defined for the register variant of the instruction (SSHL, USHL) as being right shifts. Since we have a right shift by immediate I rewrite those cases into right shifts So: int64x1_t foo3 (int64x1_t a) { return vshl_s64 (a, vdup_n_s64(-6)); } produces: foo3: sshr d0, d0, 6 ret instead of: foo3: mov x0, -6 fmov d1, x0 sshl d0, d0, d1 ret This behavior isn't specifically mentioned for a left shift by immediate, but I believe that only the case because we do have a right shift by immediate but not a right shift by register. As such I do the same for left shift by immediate. The testsuite already has various testcases for shifts (vshl.c etc) so I am not adding overlapping tests here. Out of range shifts like int64x1_t foo3 (int64x1_t a) { return vshl_s64 (a, vdup_n_s64(80)); } now get optimized to 0 as well along with undefined behaviors both in C and AArch64. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for master? Thanks, Tamar gcc/ChangeLog: * config/aarch64/aarch64-builtins.c (aarch64_general_gimple_fold_builtin): Add ashl, sshl, ushl, ashr, ashr_simd, lshr, lshr_simd. * config/aarch64/aarch64-simd-builtins.def (lshr): Use USHIFTIMM. * config/aarch64/arm_neon.h (vshr_n_u8, vshr_n_u16, vshr_n_u32, vshrq_n_u8, vshrq_n_u16, vshrq_n_u32, vshrq_n_u64): Fix type hack. gcc/testsuite/ChangeLog: * gcc.target/aarch64/signbit-2.c: New test. --- inline copy of patch -- diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c index f6b41d9c200d6300dee65ba60ae94488231a8a38..e47545b111762b95242d8f8de1a26f7bd11992ae 100644 diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c index f6b41d9c200d6300dee65ba60ae94488231a8a38..e47545b111762b95242d8f8de1a26f7bd11992ae 100644 --- a/gcc/config/aarch64/aarch64-builtins.c +++ b/gcc/config/aarch64/aarch64-builtins.c @@ -2394,6 +2394,68 @@ aarch64_general_gimple_fold_builtin (unsigned int fcode, gcall *stmt) 1, args[0]); gimple_call_set_lhs (new_stmt, gimple_call_lhs (stmt)); break; + BUILTIN_VSDQ_I_DI (BINOP, ashl, 3, NONE) + { + tree cst = args[1]; + tree ctype = TREE_TYPE (cst); + if (INTEGRAL_TYPE_P (ctype) + && TREE_CODE (cst) == INTEGER_CST) + { + wide_int wcst = wi::to_wide (cst); + if (wi::neg_p (wcst, TYPE_SIGN (ctype))) + new_stmt = + gimple_build_assign (gimple_call_lhs (stmt), + RSHIFT_EXPR, args[0], + wide_int_to_tree (ctype, + wi::abs (wcst))); + else + new_stmt = + gimple_build_assign (gimple_call_lhs (stmt), + LSHIFT_EXPR, args[0], args[1]); + } + } + break; + BUILTIN_VSDQ_I_DI (BINOP, sshl, 0, NONE) + BUILTIN_VSDQ_I_DI (BINOP_UUS, ushl, 0, NONE) + { + tree cst = args[1]; + tree ctype = TREE_TYPE (cst); + HOST_WIDE_INT bits = GET_MODE_UNIT_BITSIZE (TYPE_MODE (TREE_TYPE (args[0]))); + if (INTEGRAL_TYPE_P (ctype) + && TREE_CODE (cst) == INTEGER_CST) + { + wide_int wcst = wi::to_wide (cst); + wide_int abs_cst = wi::abs (wcst); + if (wi::eq_p (abs_cst, bits)) + break; + + if (wi::neg_p (wcst, TYPE_SIGN (ctype))) + new_stmt = + gimple_build_assign (gimple_call_lhs (stmt), + RSHIFT_EXPR, args[0], + wide_int_to_tree (ctype, abs_cst)); + else + new_stmt = + gimple_build_assign (gimple_call_lhs (stmt), + LSHIFT_EXPR, args[0], args[1]); + } + } + break; + BUILTIN_VDQ_I (SHIFTIMM, ashr, 3, NONE) + VAR1 (SHIFTIMM, ashr_simd, 0, NONE, di) + BUILTIN_VDQ_I (USHIFTIMM, lshr, 3, NONE) + VAR1 (USHIFTIMM, lshr_simd, 0, NONE, di) + { + tree cst = args[1]; + tree ctype = TREE_TYPE (cst); + HOST_WIDE_INT bits = GET_MODE_UNIT_BITSIZE (TYPE_MODE (TREE_TYPE (args[0]))); + if (INTEGRAL_TYPE_P (ctype) + && TREE_CODE (cst) == INTEGER_CST + && wi::ne_p (wi::to_wide (cst), bits)) + new_stmt = gimple_build_assign (gimple_call_lhs (stmt), + RSHIFT_EXPR, args[0], args[1]); + } + break; BUILTIN_GPF (BINOP, fmulx, 0, ALL) { gcc_assert (nargs == 2); diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index 402453aa9bba5949da43c984c4603196b1efd092..bbe0a4a3c4aea4187e7b1a9f10ab60e79df7b138 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -409,7 +409,7 @@ BUILTIN_VDQ_I (SHIFTIMM, ashr, 3, NONE) VAR1 (SHIFTIMM, ashr_simd, 0, NONE, di) - BUILTIN_VDQ_I (SHIFTIMM, lshr, 3, NONE) + BUILTIN_VDQ_I (USHIFTIMM, lshr, 3, NONE) VAR1 (USHIFTIMM, lshr_simd, 0, NONE, di) /* Implemented by aarch64_shr_n. */ BUILTIN_VSDQ_I_DI (SHIFTIMM, srshr_n, 0, NONE) diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index 635a223b59eb0f64304351939d444411b697af81..c4ef5f7f7e3658c830893931ef5a874842410e10 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -27400,21 +27400,21 @@ __extension__ extern __inline uint8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vshr_n_u8 (uint8x8_t __a, const int __b) { - return (uint8x8_t) __builtin_aarch64_lshrv8qi ((int8x8_t) __a, __b); + return __builtin_aarch64_lshrv8qi_uus (__a, __b); } __extension__ extern __inline uint16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vshr_n_u16 (uint16x4_t __a, const int __b) { - return (uint16x4_t) __builtin_aarch64_lshrv4hi ((int16x4_t) __a, __b); + return __builtin_aarch64_lshrv4hi_uus (__a, __b); } __extension__ extern __inline uint32x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vshr_n_u32 (uint32x2_t __a, const int __b) { - return (uint32x2_t) __builtin_aarch64_lshrv2si ((int32x2_t) __a, __b); + return __builtin_aarch64_lshrv2si_uus (__a, __b); } __extension__ extern __inline uint64x1_t @@ -27456,28 +27456,28 @@ __extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vshrq_n_u8 (uint8x16_t __a, const int __b) { - return (uint8x16_t) __builtin_aarch64_lshrv16qi ((int8x16_t) __a, __b); + return __builtin_aarch64_lshrv16qi_uus (__a, __b); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vshrq_n_u16 (uint16x8_t __a, const int __b) { - return (uint16x8_t) __builtin_aarch64_lshrv8hi ((int16x8_t) __a, __b); + return __builtin_aarch64_lshrv8hi_uus (__a, __b); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vshrq_n_u32 (uint32x4_t __a, const int __b) { - return (uint32x4_t) __builtin_aarch64_lshrv4si ((int32x4_t) __a, __b); + return __builtin_aarch64_lshrv4si_uus (__a, __b); } __extension__ extern __inline uint64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vshrq_n_u64 (uint64x2_t __a, const int __b) { - return (uint64x2_t) __builtin_aarch64_lshrv2di ((int64x2_t) __a, __b); + return __builtin_aarch64_lshrv2di_uus (__a, __b); } __extension__ extern __inline int64_t diff --git a/gcc/testsuite/gcc.target/aarch64/signbit-2.c b/gcc/testsuite/gcc.target/aarch64/signbit-2.c new file mode 100644 index 0000000000000000000000000000000000000000..e4e9afc854317cb599fa8118a1117c5a52e6f497 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/signbit-2.c @@ -0,0 +1,36 @@ +/* { dg-do assemble } */ +/* { dg-options "-O1 --save-temps" } */ + +#include + +int32x2_t foo1 (int32x2_t a) +{ + return vshr_n_s32 (vneg_s32 (a), 31); +} + +int32x4_t foo2 (int32x4_t a) +{ + return vshrq_n_s32 (vnegq_s32 (a), 31); +} + +int16x8_t foo3 (int16x8_t a) +{ + return vshrq_n_s16 (vnegq_s16 (a), 15); +} + +int16x4_t foo4 (int16x4_t a) +{ + return vshr_n_s16 (vneg_s16 (a), 15); +} + +int8x16_t foo5 (int8x16_t a) +{ + return vshrq_n_s8 (vnegq_s8 (a), 7); +} + +int8x8_t foo6 (int8x8_t a) +{ + return vshr_n_s8 (vneg_s8 (a), 7); +} + +/* { dg-final { scan-assembler-times {\tcmgt\t} 6 } } */