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Mon, 19 Feb 2024 20:26:51 -0800 (PST) Received: from free.home ([2804:7f1:218a:c88b:e868:4eaf:8258:c30b]) by smtp.gmail.com with ESMTPSA id u21-20020aa78395000000b006e0ad616be3sm5737290pfm.110.2024.02.19.20.26.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Feb 2024 20:26:50 -0800 (PST) Received: from livre (livre.home [172.31.160.2]) by free.home (8.15.2/8.15.2) with ESMTPS id 41K4QdQG006076 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Tue, 20 Feb 2024 01:26:39 -0300 From: Alexandre Oliva To: gcc-patches@gcc.gnu.org Cc: Kito Cheng , Palmer Dabbelt , Andrew Waterman , Jim Wilson , Raphael Moreira Zinsly Subject: [PATCH] RISC-V: Fix CTZ unnecessary sign extension [PR #106888] Organization: Free thinker, does not speak for AdaCore Date: Tue, 20 Feb 2024 01:26:39 -0300 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/27.1 (gnu/linux) MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, WEIRD_QUOTING autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org This backport for gcc-13 is required for pr90838.c to get the expected count of andi instructions on riscv64-elf, rather than fail because of two extra andi insns in functions where it is not necessary. (On riscv32-elf, it passes). Regstrapped on x86_64-linux-gnu, along with other backports, and tested manually on riscv64-elf. Ok to install? From: Raphael Moreira Zinsly Changes since v1: - Remove subreg from operand 1. -- >8 -- We were not able to match the CTZ sign extend pattern on RISC-V because it gets optimized to zero extend and/or to ANDI patterns. For the ANDI case, combine scrambles the RTL and generates the extension by using subregs. gcc/ChangeLog: PR target/106888 * config/riscv/bitmanip.md (disi2): Match with any_extend. (disi2_sext): New pattern to match with sign extend using an ANDI instruction. gcc/testsuite/ChangeLog: PR target/106888 * gcc.target/riscv/pr106888.c: New test. * gcc.target/riscv/zbbw.c: Check for ANDI. (cherry picked from commit 9000da00dd70988f30d43806bae33b22ee6b9904) --- gcc/config/riscv/bitmanip.md | 13 ++++++++++++- gcc/testsuite/gcc.target/riscv/pr106888.c | 12 ++++++++++++ gcc/testsuite/gcc.target/riscv/zbbw.c | 1 + 3 files changed, 25 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/pr106888.c diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 7aa591689ba87..cc55ca133c3fe 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -246,13 +246,24 @@ (define_insn "*si2" (define_insn "*disi2" [(set (match_operand:DI 0 "register_operand" "=r") - (sign_extend:DI + (any_extend:DI (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r"))))] "TARGET_64BIT && TARGET_ZBB" "w\t%0,%1" [(set_attr "type" "bitmanip") (set_attr "mode" "SI")]) +;; A SImode clz_ctz_pcnt may be extended to DImode via subreg. +(define_insn "*disi2_sext" + [(set (match_operand:DI 0 "register_operand" "=r") + (and:DI (subreg:DI + (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r")) 0) + (match_operand:DI 2 "const_int_operand")))] + "TARGET_64BIT && TARGET_ZBB && ((INTVAL (operands[2]) & 0x3f) == 0x3f)" + "w\t%0,%1" + [(set_attr "type" "bitmanip") + (set_attr "mode" "SI")]) + (define_insn "*di2" [(set (match_operand:DI 0 "register_operand" "=r") (clz_ctz_pcnt:DI (match_operand:DI 1 "register_operand" "r")))] diff --git a/gcc/testsuite/gcc.target/riscv/pr106888.c b/gcc/testsuite/gcc.target/riscv/pr106888.c new file mode 100644 index 0000000000000..77fb8e5b79c6b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr106888.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zbb -mabi=lp64" } */ + +int +ctz (int i) +{ + int res = __builtin_ctz (i); + return res&0xffff; +} + +/* { dg-final { scan-assembler-times "ctzw" 1 } } */ +/* { dg-final { scan-assembler-not "andi" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbbw.c b/gcc/testsuite/gcc.target/riscv/zbbw.c index 709743c3b6807..f7b2b63853f40 100644 --- a/gcc/testsuite/gcc.target/riscv/zbbw.c +++ b/gcc/testsuite/gcc.target/riscv/zbbw.c @@ -23,3 +23,4 @@ popcount (int i) /* { dg-final { scan-assembler-times "clzw" 1 } } */ /* { dg-final { scan-assembler-times "ctzw" 1 } } */ /* { dg-final { scan-assembler-times "cpopw" 1 } } */ +/* { dg-final { scan-assembler-not "andi\t" } } */