From patchwork Fri Dec 2 09:29:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Oliva X-Patchwork-Id: 61351 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 522103858417 for ; Fri, 2 Dec 2022 09:30:32 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 522103858417 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1669973432; bh=BbcUa+3PozpyGRoWzxBkAyXUGwbQbVasI2h21RlQKX8=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=btCrbd03Ydhtg+fnDEuHM/c7G7YX6eoKTuE2y3Ui9Si+oh4dfLyHhIocsoU2XDvxF S2Jh4KQa6YrwOXmiuEMDA9z42156u42fNmfk1gzJKx/NYE3qiXefmqQGuC8rlscc91 XoDHEd9DU0TPR5Wf7dawLdohrkaY/tN9WtxQjKcc= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from rock.gnat.com (rock.gnat.com [205.232.38.15]) by sourceware.org (Postfix) with ESMTPS id 800923858C52 for ; Fri, 2 Dec 2022 09:29:58 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 800923858C52 Received: from localhost (localhost.localdomain [127.0.0.1]) by filtered-rock.gnat.com (Postfix) with ESMTP id 5602A116B1E; Fri, 2 Dec 2022 04:29:58 -0500 (EST) X-Virus-Scanned: Debian amavisd-new at gnat.com Received: from rock.gnat.com ([127.0.0.1]) by localhost (rock.gnat.com [127.0.0.1]) (amavisd-new, port 10024) with LMTP id FrsjjcfIALhZ; Fri, 2 Dec 2022 04:29:58 -0500 (EST) Received: from free.home (tron.gnat.com [IPv6:2620:20:4000:0:46a8:42ff:fe0e:e294]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by rock.gnat.com (Postfix) with ESMTPS id 0B01C116562; Fri, 2 Dec 2022 04:29:57 -0500 (EST) Received: from livre (livre.home [172.31.160.2]) by free.home (8.15.2/8.15.2) with ESMTPS id 2B29Tn0d1291384 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Fri, 2 Dec 2022 06:29:49 -0300 To: gcc-patches@gcc.gnu.org Cc: Nick Clifton , Richard Earnshaw , Ramana Radhakrishnan , Kyrylo Tkachov Subject: [PATCH] [PR40457] [arm] expand SI-aligned movdi into pair of movsi Organization: Free thinker, does not speak for AdaCore Date: Fri, 02 Dec 2022 06:29:49 -0300 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Alexandre Oliva via Gcc-patches From: Alexandre Oliva Reply-To: Alexandre Oliva Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" When expanding a misaligned DImode move, emit aligned SImode moves if the parts are sufficiently aligned. This enables neighboring stores to be peephole-combined into stm, as expected by the PR40457 testcase, even after SLP vectorizes the originally aligned SImode stores into a misaligned DImode store. Regstraped on x86_64-linux-gnu, also tested with crosses to riscv64-elf and arm-eabi (tms570). Ok to install? for gcc/ChangeLog PR target/40457 * config/arm/arm.md (movmisaligndi): Prefer aligned SImode moves. --- gcc/config/arm/arm.md | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 69bf343fb0ed6..a9eb0299aa761 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -12783,8 +12783,16 @@ (define_expand "movmisaligndi" rtx hi_op0 = gen_highpart_mode (SImode, DImode, operands[0]); rtx hi_op1 = gen_highpart_mode (SImode, DImode, operands[1]); - emit_insn (gen_movmisalignsi (lo_op0, lo_op1)); - emit_insn (gen_movmisalignsi (hi_op0, hi_op1)); + if (aligned_operand (lo_op0, SImode) && aligned_operand (lo_op1, SImode)) + { + emit_move_insn (lo_op0, lo_op1); + emit_move_insn (hi_op0, hi_op1); + } + else + { + emit_insn (gen_movmisalignsi (lo_op0, lo_op1)); + emit_insn (gen_movmisalignsi (hi_op0, hi_op1)); + } DONE; })