From patchwork Sun Mar 27 22:21:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Oliva X-Patchwork-Id: 52392 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A31613857C48 for ; Sun, 27 Mar 2022 22:21:45 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A31613857C48 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1648419705; bh=aAP1iGqSGTh8HRD/uJTqrStx4d8FpPzD0KnfmnbcXIc=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=OoeDGgNK8HzJnqMORAsHUE/pVTh2XFN5DOCY3pYCLu6bWG5BgfGLR347Okrb7NbZn nqDB96+LBtN4cv6FvTwoVz13uCG9YBTHAsGoaHj9JlmZeuE67U1FwtF7Z2hQZcyQbp vFRUZJyj7ltzs139Q88iQrJ1eetn/ww86FvIwUT4= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from rock.gnat.com (rock.gnat.com [205.232.38.15]) by sourceware.org (Postfix) with ESMTPS id 48DC13858C52 for ; Sun, 27 Mar 2022 22:21:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 48DC13858C52 Received: from localhost (localhost.localdomain [127.0.0.1]) by filtered-rock.gnat.com (Postfix) with ESMTP id 19F9211673E; Sun, 27 Mar 2022 18:21:15 -0400 (EDT) X-Virus-Scanned: Debian amavisd-new at gnat.com Received: from rock.gnat.com ([127.0.0.1]) by localhost (rock.gnat.com [127.0.0.1]) (amavisd-new, port 10024) with LMTP id qpmW-LsjoStZ; Sun, 27 Mar 2022 18:21:15 -0400 (EDT) Received: from free.home (tron.gnat.com [IPv6:2620:20:4000:0:46a8:42ff:fe0e:e294]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by rock.gnat.com (Postfix) with ESMTPS id B64E01166F2; Sun, 27 Mar 2022 18:21:14 -0400 (EDT) Received: from livre (livre.home [172.31.160.2]) by free.home (8.15.2/8.15.2) with ESMTPS id 22RML6R91604531 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 27 Mar 2022 19:21:07 -0300 To: gcc-patches@gcc.gnu.org Subject: try multi dest registers in default_zero_call_used_regs Organization: Free thinker, does not speak for AdaCore Date: Sun, 27 Mar 2022 19:21:06 -0300 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.2 (gnu/linux) MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Alexandre Oliva via Gcc-patches From: Alexandre Oliva Reply-To: Alexandre Oliva Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" When the mode of regno_reg_rtx is not hard_regno_mode_ok for the target, try grouping the register with subsequent ones. This enables s16 to s31 and their hidden pairs to be zeroed with the default logic on some arm variants. Regstrapped on x86_64-linux-gnu, also tested on an affected arm configuration. Ok to install? for gcc/ChangeLog * targhooks.c (default_zero_call_used_regs): Attempt to group regs that the target refuses to use in their natural modes. --- gcc/targhooks.cc | 79 ++++++++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 70 insertions(+), 9 deletions(-) diff --git a/gcc/targhooks.cc b/gcc/targhooks.cc index fc49235eb38ee..bdaab9c63c7ee 100644 --- a/gcc/targhooks.cc +++ b/gcc/targhooks.cc @@ -1035,16 +1035,45 @@ default_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs) if (TEST_HARD_REG_BIT (need_zeroed_hardregs, regno)) { rtx_insn *last_insn = get_last_insn (); - machine_mode mode = GET_MODE (regno_reg_rtx[regno]); + rtx regno_rtx = regno_reg_rtx[regno]; + machine_mode mode = GET_MODE (regno_rtx); + + /* If the natural mode doesn't work, try some wider mode. */ + if (!targetm.hard_regno_mode_ok (regno, mode)) + { + for (int nregs = 2; + regno + nregs <= FIRST_PSEUDO_REGISTER + && TEST_HARD_REG_BIT (need_zeroed_hardregs, + regno + nregs - 1); + nregs++) + { + mode = choose_hard_reg_mode (regno, nregs, 0); + if (mode == E_VOIDmode) + continue; + gcc_checking_assert (targetm.hard_regno_mode_ok (regno, mode)); + regno_rtx = gen_rtx_REG (mode, regno); + break; + } + if (mode != GET_MODE (regno_rtx) + || regno_rtx == regno_reg_rtx[regno]) + { + SET_HARD_REG_BIT (failed, regno); + continue; + } + } + rtx zero = CONST0_RTX (mode); - rtx_insn *insn = emit_move_insn (regno_reg_rtx[regno], zero); + rtx_insn *insn = emit_move_insn (regno_rtx, zero); if (!valid_insn_p (insn)) { SET_HARD_REG_BIT (failed, regno); delete_insns_since (last_insn); } else - progress = true; + { + progress = true; + regno += hard_regno_nregs (regno, mode) - 1; + } } /* Now retry with copies from zeroed registers, as long as we've @@ -1060,7 +1089,34 @@ default_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs) for (unsigned int regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) if (TEST_HARD_REG_BIT (retrying, regno)) { - machine_mode mode = GET_MODE (regno_reg_rtx[regno]); + rtx regno_rtx = regno_reg_rtx[regno]; + machine_mode mode = GET_MODE (regno_rtx); + + /* If the natural mode doesn't work, try some wider mode. */ + if (!targetm.hard_regno_mode_ok (regno, mode)) + { + for (int nregs = 2; + regno + nregs <= FIRST_PSEUDO_REGISTER + && TEST_HARD_REG_BIT (need_zeroed_hardregs, + regno + nregs - 1); + nregs++) + { + mode = choose_hard_reg_mode (regno, nregs, 0); + if (mode == E_VOIDmode) + continue; + gcc_checking_assert (targetm.hard_regno_mode_ok (regno, + mode)); + regno_rtx = gen_rtx_REG (mode, regno); + break; + } + if (mode != GET_MODE (regno_rtx) + || regno_rtx == regno_reg_rtx[regno]) + { + SET_HARD_REG_BIT (failed, regno); + continue; + } + } + bool success = false; /* Look for a source. */ for (unsigned int src = 0; src < FIRST_PSEUDO_REGISTER; src++) @@ -1086,8 +1142,10 @@ default_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs) /* SRC is usable, try to copy from it. */ rtx_insn *last_insn = get_last_insn (); - rtx zsrc = gen_rtx_REG (mode, src); - rtx_insn *insn = emit_move_insn (regno_reg_rtx[regno], zsrc); + rtx src_rtx = (mode == GET_MODE (regno_reg_rtx[src]) + ? regno_reg_rtx[src] + : gen_rtx_REG (mode, src)); + rtx_insn *insn = emit_move_insn (regno_rtx, src_rtx); if (!valid_insn_p (insn)) /* It didn't work, remove any inserts. We'll look for another SRC. */ @@ -1100,13 +1158,16 @@ default_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs) } } - /* If nothing worked for REGNO this round, marked it to be + /* If nothing worked for REGNO this round, mark it to be retried if we get another round. */ if (!success) SET_HARD_REG_BIT (failed, regno); else - /* Take note so as to enable another round if needed. */ - progress = true; + { + /* Take note so as to enable another round if needed. */ + progress = true; + regno += hard_regno_nregs (regno, mode) - 1; + } } }