diff mbox series

riscv: add mising masking in lrsc expander (PR118137)

Message ID mvmr05eprd0.fsf@suse.de
State New
Headers
Series riscv: add mising masking in lrsc expander (PR118137) |

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Commit Message

Andreas Schwab Jan. 7, 2025, 3:37 p.m. UTC 
  gcc:
	PR target/118137
	* config/riscv/sync.md ("lrsc_atomic_exchange<mode>"): Apply mask
	to shifted value.

gcc/testsuite:
	PR target/118137
	* gcc.dg/atomic/pr118137.c: New.
---
 gcc/config/riscv/sync.md               |  1 +
 gcc/testsuite/gcc.dg/atomic/pr118137.c | 29 ++++++++++++++++++++++++++
 2 files changed, 30 insertions(+)
 create mode 100644 gcc/testsuite/gcc.dg/atomic/pr118137.c

Comments

Patrick O'Neill Jan. 7, 2025, 4:11 p.m. UTC | #1 
On 1/7/25 07:37, Andreas Schwab wrote:
> gcc:
> 	PR target/118137
> 	* config/riscv/sync.md ("lrsc_atomic_exchange<mode>"): Apply mask
> 	to shifted value.
>
> gcc/testsuite:
> 	PR target/118137
> 	* gcc.dg/atomic/pr118137.c: New.
> ---
Thanks for fixing this - I can't give approvals but LGTM FWIW.
Kito Cheng Jan. 7, 2025, 4:32 p.m. UTC | #2 
LGTM

Patrick O'Neill <patrick@rivosinc.com> 於 2025年1月8日 週三 00:12 寫道：

>
> On 1/7/25 07:37, Andreas Schwab wrote:
> > gcc:
> >       PR target/118137
> >       * config/riscv/sync.md ("lrsc_atomic_exchange<mode>"): Apply mask
> >       to shifted value.
> >
> > gcc/testsuite:
> >       PR target/118137
> >       * gcc.dg/atomic/pr118137.c: New.
> > ---
> Thanks for fixing this - I can't give approvals but LGTM FWIW.
>
Jeff Law Jan. 7, 2025, 7:25 p.m. UTC | #3 
On 1/7/25 8:37 AM, Andreas Schwab wrote:
> gcc:
> 	PR target/118137
> 	* config/riscv/sync.md ("lrsc_atomic_exchange<mode>"): Apply mask
> 	to shifted value.
> 
> gcc/testsuite:
> 	PR target/118137
> 	* gcc.dg/atomic/pr118137.c: New.
Thanks.  I went ahead and pushed this to the trunk.

jeff
Andreas Schwab Jan. 8, 2025, 9:01 a.m. UTC | #4 
Please fix your git to strip the subject prefix.
diff mbox series

Patch

diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index 58f32d253f1..726800a9662 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -467,6 +467,7 @@ 
 
   rtx shifted_value = gen_reg_rtx (SImode);
   riscv_lshift_subword (<MODE>mode, value, shift, &shifted_value);
+  emit_move_insn (shifted_value, gen_rtx_AND (SImode, shifted_value, mask));
 
   emit_insn (gen_subword_atomic_exchange_strong (old, aligned_mem,
 						 shifted_value, model,
diff --git a/gcc/testsuite/gcc.dg/atomic/pr118137.c b/gcc/testsuite/gcc.dg/atomic/pr118137.c
new file mode 100644
index 00000000000..7cdb2240aa3
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/atomic/pr118137.c
@@ -0,0 +1,29 @@ 
+/* Test that subword atomic operations only affect the subword.  */
+/* { dg-do run } */
+/* { dg-require-effective-target sync_char_short } */
+
+void
+foo (char *x)
+{
+  __sync_fetch_and_or (x, 0xff);
+}
+
+void
+bar (short *y)
+{
+  __atomic_fetch_or (y, 0xffff, 0);
+}
+
+
+int
+main ()
+{
+  char b[4] = {};
+  foo(b);
+
+  short h[2] = {};
+  bar(h);
+
+  if (b[1] || b[2] || b[3] || h[1])
+    __builtin_abort();
+}