From patchwork Sun Nov 13 10:01:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 60512 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 25C0D3898510 for ; Sun, 13 Nov 2022 10:03:09 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 25C0D3898510 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1668333789; bh=huMi7uiM5o/hSAJAiXgs1eIdOdlSvVDdknAAbp8U9U0=; h=To:Subject:References:Date:In-Reply-To:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=nBip2mIyexHXMCAFyP1rNr5JWounp+vpqIXdwYq/Botkxi4IBIAfcdx4aFcTcY6J0 XE31tjJQcvL/gucpe1ZsMoyJpNeJuHdeJiR+Q3BY9LLpSrR8NRx1sXbfwVgkuwKRRk B7AJYDc+1ku/a9dxhY87XyA3drkgCmPAnaNVSttI= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 9D8A53893663 for ; Sun, 13 Nov 2022 10:01:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 9D8A53893663 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8CD7123A for ; Sun, 13 Nov 2022 02:01:34 -0800 (PST) Received: from localhost (e121540-lin.manchester.arm.com [10.32.98.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F19D93F73D for ; Sun, 13 Nov 2022 02:01:27 -0800 (PST) To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [PATCH 07/16] aarch64: Add a register class for w12-w15 References: Date: Sun, 13 Nov 2022 10:01:26 +0000 In-Reply-To: (Richard Sandiford's message of "Sun, 13 Nov 2022 09:59:23 +0000") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 X-Spam-Status: No, score=-41.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_NUMSUBJECT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Sandiford via Gcc-patches From: Richard Sandiford Reply-To: Richard Sandiford Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Some SME instructions use w12-w15 to index ZA. This patch adds a register class for that range. gcc/ * config/aarch64/aarch64.h (ZA_INDEX_REGNUM_P): New macro. (ZA_INDEX_REGS): New register class. (REG_CLASS_NAMES, REG_CLASS_CONTENTS): Add entries for it. * config/aarch64/aarch64.cc (aarch64_regno_regclass) (aarch64_class_max_nregs, aarch64_register_move_cost): Handle ZA_INDEX_REGS. --- gcc/config/aarch64/aarch64.cc | 12 +++++++----- gcc/config/aarch64/aarch64.h | 6 ++++++ 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index b200d2a9f80..d29cfefee6b 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -13553,6 +13553,9 @@ aarch64_label_mentioned_p (rtx x) enum reg_class aarch64_regno_regclass (unsigned regno) { + if (ZA_INDEX_REGNUM_P (regno)) + return ZA_INDEX_REGS; + if (STUB_REGNUM_P (regno)) return STUB_REGS; @@ -13917,6 +13920,7 @@ aarch64_class_max_nregs (reg_class_t regclass, machine_mode mode) unsigned int nregs, vec_flags; switch (regclass) { + case ZA_INDEX_REGS: case STUB_REGS: case TAILCALL_ADDR_REGS: case POINTER_REGS: @@ -16252,13 +16256,11 @@ aarch64_register_move_cost (machine_mode mode, const struct cpu_regmove_cost *regmove_cost = aarch64_tune_params.regmove_cost; - /* Caller save and pointer regs are equivalent to GENERAL_REGS. */ - if (to == TAILCALL_ADDR_REGS || to == POINTER_REGS - || to == STUB_REGS) + /* Trest any subset of GENERAL_REGS as though it were GENERAL_REGS. */ + if (reg_class_subset_p (to, GENERAL_REGS)) to = GENERAL_REGS; - if (from == TAILCALL_ADDR_REGS || from == POINTER_REGS - || from == STUB_REGS) + if (reg_class_subset_p (from, GENERAL_REGS)) from = GENERAL_REGS; /* Make RDFFR very expensive. In particular, if we know that the FFR diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index b5877e7e61e..bfa28726221 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -643,6 +643,9 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE = AARCH64_FL_SM_OFF; && (REGNO) != R17_REGNUM \ && (REGNO) != R30_REGNUM) \ +#define ZA_INDEX_REGNUM_P(REGNO) \ + IN_RANGE (REGNO, R12_REGNUM, R15_REGNUM) + #define FP_REGNUM_P(REGNO) \ (((unsigned) (REGNO - V0_REGNUM)) <= (V31_REGNUM - V0_REGNUM)) @@ -666,6 +669,7 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE = AARCH64_FL_SM_OFF; enum reg_class { NO_REGS, + ZA_INDEX_REGS, TAILCALL_ADDR_REGS, STUB_REGS, GENERAL_REGS, @@ -690,6 +694,7 @@ enum reg_class #define REG_CLASS_NAMES \ { \ "NO_REGS", \ + "ZA_INDEX_REGS", \ "TAILCALL_ADDR_REGS", \ "STUB_REGS", \ "GENERAL_REGS", \ @@ -711,6 +716,7 @@ enum reg_class #define REG_CLASS_CONTENTS \ { \ { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ + { 0x0000f000, 0x00000000, 0x00000000 }, /* ZA_INDEX_REGS */ \ { 0x00030000, 0x00000000, 0x00000000 }, /* TAILCALL_ADDR_REGS */\ { 0x3ffcffff, 0x00000000, 0x00000000 }, /* STUB_REGS */ \ { 0x7fffffff, 0x00000000, 0x00000003 }, /* GENERAL_REGS */ \