From patchwork Wed Feb 9 17:01:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 50967 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 54B643858D3C for ; Wed, 9 Feb 2022 17:08:10 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 54B643858D3C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1644426490; bh=ijOwJHFr6Pho0DFzb7BV+84M1i0U09q4ZiKIF12soWg=; h=To:Subject:References:Date:In-Reply-To:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=uOL7+e+Lbxtrf4kZDn88U3cpLcESo4bkXG+07UeXomEu38zQzpIrMDwznGfv1QO7j Sy96a3Taq80pLgJvwZ4LyFHHi7jcrGlBMRrHyohKml1E+1mWXW6wVzZV3K68clZDoz h2/j8XUuUD7Z2m3udZdOyPim8KdeKcFcBL0FO2hU= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 25CD13857815 for ; Wed, 9 Feb 2022 17:02:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 25CD13857815 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D5CD4ED1 for ; Wed, 9 Feb 2022 09:02:01 -0800 (PST) Received: from localhost (unknown [10.32.98.88]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6A42B3F73B for ; Wed, 9 Feb 2022 09:02:01 -0800 (PST) To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [pushed 7/8] aarch64: Remove move_lo/hi_quad expanders References: Date: Wed, 09 Feb 2022 17:01:59 +0000 In-Reply-To: (Richard Sandiford's message of "Wed, 09 Feb 2022 17:00:03 +0000") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Sandiford via Gcc-patches From: Richard Sandiford Reply-To: Richard Sandiford Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This patch is the second of two to remove the old move_lo/hi_quad expanders and move_hi_quad insns. gcc/ * config/aarch64/aarch64-simd.md (@aarch64_split_simd_mov): Use aarch64_combine instead of move_lo/hi_quad. Tabify. (move_lo_quad_, aarch64_simd_move_hi_quad_): Delete. (aarch64_simd_move_hi_quad_be_, move_hi_quad_): Delete. (vec_pack_trunc_): Take general_operand elements and use aarch64_combine rather than move_lo/hi_quad to combine them. (vec_pack_trunc_df): Likewise. --- gcc/config/aarch64/aarch64-simd.md | 111 +++++------------------------ 1 file changed, 18 insertions(+), 93 deletions(-) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 7acde0dd099..ef6e772503d 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -272,7 +272,7 @@ (define_split (define_expand "@aarch64_split_simd_mov" [(set (match_operand:VQMOV 0) - (match_operand:VQMOV 1))] + (match_operand:VQMOV 1))] "TARGET_SIMD" { rtx dst = operands[0]; @@ -280,23 +280,22 @@ (define_expand "@aarch64_split_simd_mov" if (GP_REGNUM_P (REGNO (src))) { - rtx src_low_part = gen_lowpart (mode, src); - rtx src_high_part = gen_highpart (mode, src); + rtx src_low_part = gen_lowpart (mode, src); + rtx src_high_part = gen_highpart (mode, src); + rtx dst_low_part = gen_lowpart (mode, dst); - emit_insn - (gen_move_lo_quad_ (dst, src_low_part)); - emit_insn - (gen_move_hi_quad_ (dst, src_high_part)); + emit_move_insn (dst_low_part, src_low_part); + emit_insn (gen_aarch64_combine (dst, dst_low_part, + src_high_part)); } - else { - rtx dst_low_part = gen_lowpart (mode, dst); - rtx dst_high_part = gen_highpart (mode, dst); + rtx dst_low_part = gen_lowpart (mode, dst); + rtx dst_high_part = gen_highpart (mode, dst); rtx lo = aarch64_simd_vect_par_cnst_half (mode, , false); rtx hi = aarch64_simd_vect_par_cnst_half (mode, , true); - emit_insn (gen_aarch64_get_half (dst_low_part, src, lo)); - emit_insn (gen_aarch64_get_half (dst_high_part, src, hi)); + emit_insn (gen_aarch64_get_half (dst_low_part, src, lo)); + emit_insn (gen_aarch64_get_half (dst_high_part, src, hi)); } DONE; } @@ -1580,69 +1579,6 @@ (define_insn "aarch64_p" ;; What that means, is that the RTL descriptions of the below patterns ;; need to change depending on endianness. -;; Move to the low architectural bits of the register. -;; On little-endian this is { operand, zeroes } -;; On big-endian this is { zeroes, operand } - -(define_expand "move_lo_quad_" - [(match_operand:VQMOV 0 "register_operand") - (match_operand: 1 "register_operand")] - "TARGET_SIMD" -{ - emit_insn (gen_aarch64_combine (operands[0], operands[1], - CONST0_RTX (mode))); - DONE; -} -) - -;; Move operand1 to the high architectural bits of the register, keeping -;; the low architectural bits of operand2. -;; For little-endian this is { operand2, operand1 } -;; For big-endian this is { operand1, operand2 } - -(define_insn "aarch64_simd_move_hi_quad_" - [(set (match_operand:VQMOV 0 "register_operand" "+w,w") - (vec_concat:VQMOV - (vec_select: - (match_dup 0) - (match_operand:VQMOV 2 "vect_par_cnst_lo_half" "")) - (match_operand: 1 "register_operand" "w,r")))] - "TARGET_SIMD && !BYTES_BIG_ENDIAN" - "@ - ins\\t%0.d[1], %1.d[0] - ins\\t%0.d[1], %1" - [(set_attr "type" "neon_ins")] -) - -(define_insn "aarch64_simd_move_hi_quad_be_" - [(set (match_operand:VQMOV 0 "register_operand" "+w,w") - (vec_concat:VQMOV - (match_operand: 1 "register_operand" "w,r") - (vec_select: - (match_dup 0) - (match_operand:VQMOV 2 "vect_par_cnst_lo_half" ""))))] - "TARGET_SIMD && BYTES_BIG_ENDIAN" - "@ - ins\\t%0.d[1], %1.d[0] - ins\\t%0.d[1], %1" - [(set_attr "type" "neon_ins")] -) - -(define_expand "move_hi_quad_" - [(match_operand:VQMOV 0 "register_operand") - (match_operand: 1 "register_operand")] - "TARGET_SIMD" -{ - rtx p = aarch64_simd_vect_par_cnst_half (mode, , false); - if (BYTES_BIG_ENDIAN) - emit_insn (gen_aarch64_simd_move_hi_quad_be_ (operands[0], - operands[1], p)); - else - emit_insn (gen_aarch64_simd_move_hi_quad_ (operands[0], - operands[1], p)); - DONE; -}) - ;; Narrowing operations. (define_insn "aarch64_xtn_insn_le" @@ -1743,16 +1679,12 @@ (define_insn "*aarch64_narrow_trunc" (define_expand "vec_pack_trunc_" [(match_operand: 0 "register_operand") - (match_operand:VDN 1 "register_operand") - (match_operand:VDN 2 "register_operand")] + (match_operand:VDN 1 "general_operand") + (match_operand:VDN 2 "general_operand")] "TARGET_SIMD" { rtx tempreg = gen_reg_rtx (mode); - int lo = BYTES_BIG_ENDIAN ? 2 : 1; - int hi = BYTES_BIG_ENDIAN ? 1 : 2; - - emit_insn (gen_move_lo_quad_ (tempreg, operands[lo])); - emit_insn (gen_move_hi_quad_ (tempreg, operands[hi])); + emit_insn (gen_aarch64_vec_concat (tempreg, operands[1], operands[2])); emit_insn (gen_trunc2 (operands[0], tempreg)); DONE; }) @@ -3402,20 +3334,13 @@ (define_expand "vec_pack_trunc_v2df" (define_expand "vec_pack_trunc_df" [(set (match_operand:V2SF 0 "register_operand") - (vec_concat:V2SF - (float_truncate:SF - (match_operand:DF 1 "register_operand")) - (float_truncate:SF - (match_operand:DF 2 "register_operand")) - ))] + (vec_concat:V2SF + (float_truncate:SF (match_operand:DF 1 "general_operand")) + (float_truncate:SF (match_operand:DF 2 "general_operand"))))] "TARGET_SIMD" { rtx tmp = gen_reg_rtx (V2SFmode); - int lo = BYTES_BIG_ENDIAN ? 2 : 1; - int hi = BYTES_BIG_ENDIAN ? 1 : 2; - - emit_insn (gen_move_lo_quad_v2df (tmp, operands[lo])); - emit_insn (gen_move_hi_quad_v2df (tmp, operands[hi])); + emit_insn (gen_aarch64_vec_concatdf (tmp, operands[1], operands[2])); emit_insn (gen_aarch64_float_truncate_lo_v2sf (operands[0], tmp)); DONE; }