From patchwork Sun Nov 13 10:00:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 60508 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CA1353889819 for ; Sun, 13 Nov 2022 10:00:44 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org CA1353889819 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1668333644; bh=b342ph2aXKDXdanS7z32QjLuk+4UqXG4Vp80fBUGv+Q=; h=To:Subject:References:Date:In-Reply-To:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=Jb4k6/XeZRZjl6EvuFCc7Fq690YbLXcZR2eyJwL5kshycoQmEXDcc0VI12qznFNjy Et9UDQ8OHQnEs1Flaahx5HNVUgf2eAbjHlilVb46+QSKVsE6kK+TX594RkFMvhalSx vzDylqL+mO2A8/9dMympjX9UCqlMOxPntLWJZE/g= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id CBD9E3887F7D for ; Sun, 13 Nov 2022 10:00:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org CBD9E3887F7D Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BB5F923A for ; Sun, 13 Nov 2022 02:00:17 -0800 (PST) Received: from localhost (e121540-lin.manchester.arm.com [10.32.98.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2B7283F73D for ; Sun, 13 Nov 2022 02:00:11 -0800 (PST) To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [PATCH 02/16] aarch64: Add +sme References: Date: Sun, 13 Nov 2022 10:00:09 +0000 In-Reply-To: (Richard Sandiford's message of "Sun, 13 Nov 2022 09:59:23 +0000") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 X-Spam-Status: No, score=-42.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Sandiford via Gcc-patches From: Richard Sandiford Reply-To: Richard Sandiford Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This patch adds the +sme ISA feature and requires it to be present when compiling arm_streaming code. (arm_streaming_compatible code does not necessarily assume the presence of SME. It just has to work when SME is present and streaming mode is enabled.) gcc/ * doc/gcc/gcc-command-options/machine-dependent-options/aarch64-options.rst: Document SME. * doc/gccint/testsuites/directives-used-within-dejagnu-tests/keywords-describing-target-attributes.rst: Document aarch64_sve. * config/aarch64/aarch64-option-extensions.def (sme): Define. * config/aarch64/aarch64.h (AARCH64_ISA_SME): New macro. * config/aarch64/aarch64.cc (aarch64_override_options_internal): Ensure that SME is present when compiling streaming code. gcc/testsuite/ * lib/target-supports.exp (check_effective_target_aarch64_sme): New target test. * gcc.target/aarch64/sme/aarch64-sme.exp: Force SME to be enabled if it isn't by default. * gcc.target/aarch64/sme/streaming_mode_3.c: New test. --- .../aarch64/aarch64-option-extensions.def | 2 + gcc/config/aarch64/aarch64.cc | 33 ++++++++++ gcc/config/aarch64/aarch64.h | 1 + .../aarch64-options.rst | 3 + .../keywords-describing-target-attributes.rst | 3 + .../gcc.target/aarch64/sme/aarch64-sme.exp | 10 ++- .../gcc.target/aarch64/sme/streaming_mode_3.c | 63 +++++++++++++++++++ .../gcc.target/aarch64/sme/streaming_mode_4.c | 22 +++++++ gcc/testsuite/lib/target-supports.exp | 12 ++++ 9 files changed, 147 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/sme/streaming_mode_3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme/streaming_mode_4.c diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def index bdf4baf309c..402a9832f87 100644 --- a/gcc/config/aarch64/aarch64-option-extensions.def +++ b/gcc/config/aarch64/aarch64-option-extensions.def @@ -129,6 +129,8 @@ AARCH64_OPT_EXTENSION("sve2-sha3", SVE2_SHA3, (SVE2, SHA3), (), (), "svesha3") AARCH64_OPT_EXTENSION("sve2-bitperm", SVE2_BITPERM, (SVE2), (), (), "svebitperm") +AARCH64_OPT_EXTENSION("sme", SME, (SVE2), (), (), "sme") + AARCH64_OPT_EXTENSION("tme", TME, (), (), (), "") AARCH64_OPT_EXTENSION("i8mm", I8MM, (SIMD), (), (), "i8mm") diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index a2e910daddf..fc6f0bc208a 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -11374,6 +11374,23 @@ aarch64_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2) return true; } +/* Implement TARGET_START_CALL_ARGS. */ + +static void +aarch64_start_call_args (cumulative_args_t ca_v) +{ + CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v); + + if (!TARGET_SME && (ca->isa_mode & AARCH64_FL_SM_ON)) + { + error ("calling a streaming function requires the ISA extension %qs", + "sme"); + inform (input_location, "you can enable %qs using the command-line" + " option %<-march%>, or by using the %" + " attribute or pragma", "sme"); + } +} + /* This function is used by the call expanders of the machine description. RESULT is the register in which the result is returned. It's NULL for "call" and "sibcall". @@ -17865,6 +17882,19 @@ aarch64_override_options_internal (struct gcc_options *opts) && !fixed_regs[R18_REGNUM]) error ("%<-fsanitize=shadow-call-stack%> requires %<-ffixed-x18%>"); + if ((opts->x_aarch64_isa_flags & AARCH64_FL_SM_ON) + && !(opts->x_aarch64_isa_flags & AARCH64_FL_SME)) + { + error ("streaming functions require the ISA extension %qs", "sme"); + inform (input_location, "you can enable %qs using the command-line" + " option %<-march%>, or by using the %" + " attribute or pragma", "sme"); + opts->x_target_flags &= ~MASK_GENERAL_REGS_ONLY; + auto new_flags = (opts->x_aarch64_asm_isa_flags + | feature_deps::SME ().enable); + aarch64_set_asm_isa_flags (opts, new_flags); + } + initialize_aarch64_code_model (opts); initialize_aarch64_tls_size (opts); @@ -27721,6 +27751,9 @@ aarch64_run_selftests (void) #undef TARGET_FUNCTION_VALUE_REGNO_P #define TARGET_FUNCTION_VALUE_REGNO_P aarch64_function_value_regno_p +#undef TARGET_START_CALL_ARGS +#define TARGET_START_CALL_ARGS aarch64_start_call_args + #undef TARGET_GIMPLE_FOLD_BUILTIN #define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 1ac37b902bf..c47f27eefec 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -214,6 +214,7 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE = AARCH64_FL_SM_OFF; #define AARCH64_ISA_SVE2_BITPERM (aarch64_isa_flags & AARCH64_FL_SVE2_BITPERM) #define AARCH64_ISA_SVE2_SHA3 (aarch64_isa_flags & AARCH64_FL_SVE2_SHA3) #define AARCH64_ISA_SVE2_SM4 (aarch64_isa_flags & AARCH64_FL_SVE2_SM4) +#define AARCH64_ISA_SME (aarch64_isa_flags & AARCH64_FL_SME) #define AARCH64_ISA_V8_3A (aarch64_isa_flags & AARCH64_FL_V8_3A) #define AARCH64_ISA_DOTPROD (aarch64_isa_flags & AARCH64_FL_DOTPROD) #define AARCH64_ISA_AES (aarch64_isa_flags & AARCH64_FL_AES) diff --git a/gcc/doc/gcc/gcc-command-options/machine-dependent-options/aarch64-options.rst b/gcc/doc/gcc/gcc-command-options/machine-dependent-options/aarch64-options.rst index c2b23a6ee97..f6d82f4435b 100644 --- a/gcc/doc/gcc/gcc-command-options/machine-dependent-options/aarch64-options.rst +++ b/gcc/doc/gcc/gcc-command-options/machine-dependent-options/aarch64-options.rst @@ -544,6 +544,9 @@ the following and their inverses no :samp:`{feature}` : :samp:`pauth` Enable the Pointer Authentication Extension. +:samp:`sme` + Enable the Scalable Matrix Extension. + Feature ``crypto`` implies ``aes``, ``sha2``, and ``simd``, which implies ``fp``. Conversely, ``nofp`` implies ``nosimd``, which implies diff --git a/gcc/doc/gccint/testsuites/directives-used-within-dejagnu-tests/keywords-describing-target-attributes.rst b/gcc/doc/gccint/testsuites/directives-used-within-dejagnu-tests/keywords-describing-target-attributes.rst index 709e4ea2b90..84822b4335c 100644 --- a/gcc/doc/gccint/testsuites/directives-used-within-dejagnu-tests/keywords-describing-target-attributes.rst +++ b/gcc/doc/gccint/testsuites/directives-used-within-dejagnu-tests/keywords-describing-target-attributes.rst @@ -886,6 +886,9 @@ AArch64-specific attributes AArch64 target that is able to generate and execute armv8.3-a FJCVTZS instruction. +``aarch64_sme`` + AArch64 target that generates instructions for SME. + MIPS-specific attributes ~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/gcc/testsuite/gcc.target/aarch64/sme/aarch64-sme.exp b/gcc/testsuite/gcc.target/aarch64/sme/aarch64-sme.exp index c542912e14a..b3ad2ea4c5e 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme/aarch64-sme.exp +++ b/gcc/testsuite/gcc.target/aarch64/sme/aarch64-sme.exp @@ -31,10 +31,16 @@ load_lib gcc-dg.exp # Initialize `dg'. dg-init -aarch64-with-arch-dg-options "" { +if { [check_effective_target_aarch64_sme] } { + set sme_flags "" +} else { + set sme_flags "-march=armv8.2-a+sme" +} + +aarch64-with-arch-dg-options $sme_flags { # Main loop. dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \ - "" "" + "" $sme_flags } # All done. diff --git a/gcc/testsuite/gcc.target/aarch64/sme/streaming_mode_3.c b/gcc/testsuite/gcc.target/aarch64/sme/streaming_mode_3.c new file mode 100644 index 00000000000..926ffa24e45 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme/streaming_mode_3.c @@ -0,0 +1,63 @@ +// { dg-options "" } + +#pragma GCC target "+nosme" + +void __attribute__((arm_streaming_compatible)) sc_a () {} +void __attribute__((arm_streaming)) s_a () {} // { dg-error "streaming functions require the ISA extension 'sme'" } +void ns_a () {} + +void __attribute__((arm_streaming_compatible)) sc_b () {} +void ns_b () {} +void __attribute__((arm_streaming)) s_b () {} // { dg-error "streaming functions require the ISA extension 'sme'" } + +void __attribute__((arm_streaming_compatible)) sc_c () {} +void __attribute__((arm_streaming_compatible)) sc_d () {} + +void __attribute__((arm_streaming)) s_c () {} // { dg-error "streaming functions require the ISA extension 'sme'" } +void __attribute__((arm_streaming)) s_d () {} // { dg-error "streaming functions require the ISA extension 'sme'" } + +void ns_c () {} +void ns_d () {} + +void __attribute__((arm_streaming_compatible)) sc_e (); +void __attribute__((arm_streaming)) s_e (); +void ns_e (); + +#pragma GCC target "+sme" + +void __attribute__((arm_streaming_compatible)) sc_f () {} +void __attribute__((arm_streaming)) s_f () {} +void ns_f () {} + +void __attribute__((arm_streaming_compatible)) sc_g () {} +void ns_g () {} +void __attribute__((arm_streaming)) s_g () {} + +void __attribute__((arm_streaming_compatible)) sc_h () {} +void __attribute__((arm_streaming_compatible)) sc_i () {} + +void __attribute__((arm_streaming)) s_h () {} +void __attribute__((arm_streaming)) s_i () {} + +void ns_h () {} +void ns_i () {} + +void __attribute__((arm_streaming_compatible)) sc_j (); +void __attribute__((arm_streaming)) s_j (); +void ns_j (); + +#pragma GCC target "+sme" + +void __attribute__((arm_streaming_compatible)) sc_k () {} + +#pragma GCC target "+nosme" +#pragma GCC target "+sme" + +void __attribute__((arm_streaming)) s_k () {} + +#pragma GCC target "+nosme" +#pragma GCC target "+sme" + +void ns_k () {} + +#pragma GCC target "+nosme" diff --git a/gcc/testsuite/gcc.target/aarch64/sme/streaming_mode_4.c b/gcc/testsuite/gcc.target/aarch64/sme/streaming_mode_4.c new file mode 100644 index 00000000000..d777d7ee0d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme/streaming_mode_4.c @@ -0,0 +1,22 @@ +// { dg-options "-mgeneral-regs-only" } + +void __attribute__((arm_streaming_compatible)) sc_a () {} +void __attribute__((arm_streaming)) s_a () {} // { dg-error "streaming functions require the ISA extension 'sme'" } +void ns_a () {} + +void __attribute__((arm_streaming_compatible)) sc_b () {} +void ns_b () {} +void __attribute__((arm_streaming)) s_b () {} // { dg-error "streaming functions require the ISA extension 'sme'" } + +void __attribute__((arm_streaming_compatible)) sc_c () {} +void __attribute__((arm_streaming_compatible)) sc_d () {} + +void __attribute__((arm_streaming)) s_c () {} // { dg-error "streaming functions require the ISA extension 'sme'" } +void __attribute__((arm_streaming)) s_d () {} // { dg-error "streaming functions require the ISA extension 'sme'" } + +void ns_c () {} +void ns_d () {} + +void __attribute__((arm_streaming_compatible)) sc_e (); +void __attribute__((arm_streaming)) s_e (); +void ns_e (); diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index c7f583d6d14..f6cb16521b3 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -3967,6 +3967,18 @@ proc aarch64_sve_bits { } { }] } +# Return 1 if this is an AArch64 target that generates instructions for SME. +proc check_effective_target_aarch64_sme { } { + if { ![istarget aarch64*-*-*] } { + return 0 + } + return [check_no_compiler_messages aarch64_sme assembly { + #if !defined (__ARM_FEATURE_SME) + #error FOO + #endif + }] +} + # Return 1 if this is a compiler supporting ARC atomic operations proc check_effective_target_arc_atomic { } { return [check_no_compiler_messages arc_atomic assembly {