From patchwork Mon Nov 8 10:39:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 47202 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0A639385800C for ; Mon, 8 Nov 2021 10:40:06 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 0A639385800C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1636368006; bh=qC1f0D7UMSDD8t4JHmX3uwv2jGX1i1XBiRR4aQDyvT0=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=MR5zLpNEbp9f09HKbcM4Lr3DzqNTONahc3AASXCHec4XBufDWm+XgyLsysGLeKmms 6DSJDsR+KI8+/eheP6wRcXCQECXr+/G1Su04v4n2cWfzyWgq7j8qByLTqDGuhwKLN4 KdUg81l5TFHNC/40XQ8N/KKHaXIq6rHrYXagLYks= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id C1F8E3858415 for ; Mon, 8 Nov 2021 10:39:36 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org C1F8E3858415 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 73E7BD6E for ; Mon, 8 Nov 2021 02:39:36 -0800 (PST) Received: from localhost (e121540-lin.manchester.arm.com [10.32.98.88]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1AB443F800 for ; Mon, 8 Nov 2021 02:39:35 -0800 (PST) To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [committed] aarch64: LD3/LD4 post-modify costs for struct modes Date: Mon, 08 Nov 2021 10:39:34 +0000 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Sandiford via Gcc-patches From: Richard Sandiford Reply-To: Richard Sandiford Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" The LD3/ST3 and LD4/ST4 address cost code had no test coverage (oops). This patch fixes that and updates it for the new structure modes. The test only covers Advanced SIMD because SVE doesn't have post-increment forms. Tested on aarch64-linxu-gnu & pushed. Richard gcc/ * config/aarch64/aarch64.c (aarch64_ldn_stn_vectors): New function. (aarch64_address_cost): Use it instead of testing for CImode and XImode directly. gcc/testsuite/ * gcc.target/aarch64/neoverse_v1_1.c: New test. --- gcc/config/aarch64/aarch64.c | 22 +++++++++++++++++-- .../gcc.target/aarch64/neoverse_v1_1.c | 15 +++++++++++++ 2 files changed, 35 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/neoverse_v1_1.c diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index fdf05505846..19f67415234 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -3108,6 +3108,23 @@ aarch64_vl_bytes (machine_mode mode, unsigned int vec_flags) return BYTES_PER_SVE_PRED; } +/* If MODE holds an array of vectors, return the number of vectors + in the array, otherwise return 1. */ + +static unsigned int +aarch64_ldn_stn_vectors (machine_mode mode) +{ + unsigned int vec_flags = aarch64_classify_vector_mode (mode); + if (vec_flags == (VEC_ADVSIMD | VEC_PARTIAL | VEC_STRUCT)) + return exact_div (GET_MODE_SIZE (mode), 8).to_constant (); + if (vec_flags == (VEC_ADVSIMD | VEC_STRUCT)) + return exact_div (GET_MODE_SIZE (mode), 16).to_constant (); + if (vec_flags == (VEC_SVE_DATA | VEC_STRUCT)) + return exact_div (GET_MODE_SIZE (mode), + BYTES_PER_SVE_VECTOR).to_constant (); + return 1; +} + /* Given an Advanced SIMD vector mode MODE and a tuple size NELEMS, return the corresponding vector structure mode. */ static opt_machine_mode @@ -12511,9 +12528,10 @@ aarch64_address_cost (rtx x, cost += addr_cost->pre_modify; else if (c == POST_INC || c == POST_DEC || c == POST_MODIFY) { - if (mode == CImode) + unsigned int nvectors = aarch64_ldn_stn_vectors (mode); + if (nvectors == 3) cost += addr_cost->post_modify_ld3_st3; - else if (mode == XImode) + else if (nvectors == 4) cost += addr_cost->post_modify_ld4_st4; else cost += addr_cost->post_modify; diff --git a/gcc/testsuite/gcc.target/aarch64/neoverse_v1_1.c b/gcc/testsuite/gcc.target/aarch64/neoverse_v1_1.c new file mode 100644 index 00000000000..c1563f01861 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/neoverse_v1_1.c @@ -0,0 +1,15 @@ +/* { dg-options "-O2 -mcpu=neoverse-v1" } */ + +void +foo (short *restrict x, short y[restrict][128]) +{ + for (int i = 0; i < 128; ++i) + { + y[0][i] = x[i * 3 + 0]; + y[1][i] = x[i * 3 + 1]; + y[2][i] = x[i * 3 + 2]; + } +} + +/* This shouldn't be a post-increment. */ +/* { dg-final { scan-assembler {ld3\t{[^{}]*}, \[x[0-9]+\]\n} } } */