From patchwork Thu Nov 4 08:31:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 47034 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 993E53858013 for ; Thu, 4 Nov 2021 08:33:00 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 993E53858013 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1636014780; bh=++G6BtC4zD1sVwlbJ98pYCwFVSGblPs7uvqpdicMvyA=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=tlWRlAljR2HqyNo/3rtPj4AhDAnV8ymGPy6b3p8ImZmg4jV+p9L4WfT9+T2+IBhsz Leby1i/6UROqQfYE4mn/AQODG288tac7WifEOAYbpec0svDsfr5WfcBPx0Wk6nrftu TYYwAUIx8/tKARsD5+XwWhOEV+fyWJZbmJIF4VeY= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 28B943858036 for ; Thu, 4 Nov 2021 08:31:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 28B943858036 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C83461FB for ; Thu, 4 Nov 2021 01:31:50 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.98.88]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6F4683F719 for ; Thu, 4 Nov 2021 01:31:50 -0700 (PDT) To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [committed] simplify-rtx: Fix vec_select index check Date: Thu, 04 Nov 2021 08:31:49 +0000 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Sandiford via Gcc-patches From: Richard Sandiford Reply-To: Richard Sandiford Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Vector lane indices follow memory (array) order, so lane 0 corresponds to the high element rather than the low element on big-endian targets. This was causing quite a few execution failures on aarch64_be, such as gcc.c-torture/execute/pr47538.c. Tested on aarch64-linux-gnu and aarch64_be-elf. Applied as obvious. Richard gcc/ * simplify-rtx.c (simplify_context::simplify_gen_vec_select): Assert that the operand has a vector mode. Use subreg_lowpart_offset to test whether an index corresponds to the low part. gcc/testsuite/ * gcc.dg/rtl/aarch64/big-endian-cse-1.c: New test. --- gcc/simplify-rtx.c | 12 +++--- .../gcc.dg/rtl/aarch64/big-endian-cse-1.c | 42 +++++++++++++++++++ 2 files changed, 48 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/rtl/aarch64/big-endian-cse-1.c diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c index aac5693f548..9038affa036 100644 --- a/gcc/simplify-rtx.c +++ b/gcc/simplify-rtx.c @@ -7622,15 +7622,15 @@ simplify_context::lowpart_subreg (machine_mode outer_mode, rtx expr, /* Generate RTX to select element at INDEX out of vector OP. */ -rtx simplify_context::simplify_gen_vec_select (rtx op, unsigned int index) +rtx +simplify_context::simplify_gen_vec_select (rtx op, unsigned int index) { + gcc_assert (VECTOR_MODE_P (GET_MODE (op))); - if (!VECTOR_MODE_P (GET_MODE (op))) - return NULL_RTX; - - machine_mode imode = GET_MODE_INNER (GET_MODE (op)); + scalar_mode imode = GET_MODE_INNER (GET_MODE (op)); - if (index == 0) + if (known_eq (index * GET_MODE_SIZE (imode), + subreg_lowpart_offset (imode, GET_MODE (op)))) { rtx res = lowpart_subreg (imode, op, GET_MODE (op)); if (res) diff --git a/gcc/testsuite/gcc.dg/rtl/aarch64/big-endian-cse-1.c b/gcc/testsuite/gcc.dg/rtl/aarch64/big-endian-cse-1.c new file mode 100644 index 00000000000..1559a489f25 --- /dev/null +++ b/gcc/testsuite/gcc.dg/rtl/aarch64/big-endian-cse-1.c @@ -0,0 +1,42 @@ +/* { dg-do compile { target aarch64*-*-* } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O3 -mbig-endian" } */ + +void __RTL (startwith ("vregs")) foo (void *ptr1, void *ptr2) +{ + (function "foo" + (param "ptr1" + (DECL_RTL (reg/v:DI <0> [ ptr1 ])) + (DECL_RTL_INCOMING (reg:DI x0 [ ptr1 ])) + ) ;; param "ptr1" + (param "ptr2" + (DECL_RTL (reg/v:DI <1> [ ptr2 ])) + (DECL_RTL_INCOMING (reg:DI x1 [ ptr2 ])) + ) ;; param "ptr2" + (insn-chain + (block 2 + (edge-from entry (flags "FALLTHRU")) + (cnote 3 [bb 2] NOTE_INSN_BASIC_BLOCK) + (insn 4 (set (reg:DI <0>) (reg:DI x0))) + (insn 5 (set (reg:DI <1>) (reg:DI x1))) + (insn 6 (set (reg:V2SI <2>) + (const_vector:V2SI [(const_int 1) + (const_int 0)])) (nil)) + (insn 7 (set (mem:V2SI (reg:DI <0>) [1 ptr1+0 S8 A8]) + (reg:V2SI <2>))) + (insn 8 (set (reg:V4SI <3>) + (const_vector:V4SI [(const_int 1) + (const_int 1) + (const_int 1) + (const_int 1)])) (nil)) + (insn 9 (set (reg:SI <4>) (subreg:SI (reg:V4SI <3>) 12)) + (expr_list:REG_EQUAL (const_int 1) (nil))) + (insn 10 (set (mem:SI (reg:DI <1>) [1 ptr2+0 S4 A4]) + (reg:SI <4>))) + (edge-to exit (flags "FALLTHRU")) + ) ;; block 2 + ) ;; insn-chain + ) ;; function +} + +/* { dg-final { scan-assembler-not {\tstr\twzr,} } } */