From patchwork Wed Feb 9 17:01:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 50964 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D63173858C3A for ; Wed, 9 Feb 2022 17:05:08 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D63173858C3A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1644426308; bh=Hb+nGeiZq3DeRmCdSYXW+eOhJCRK4AB26PPYc3XYb6k=; h=To:Subject:References:Date:In-Reply-To:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=SlxBeQhq789NuHWiDZ5K8F3x+XuvC42JMpqFMGMt5oHPKU7Dz2G8k6rIIma0KwioO WGy5uOsqBw81e7OVPievxTG3zdqoe2bUcK8InrQsA4IAdtgic/xWZzDPnhwyZbJNVH dlDxTCLdytdN/wc1uZ06XGL+UAF2Ea4760Sxw3E0= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 35F1B3857C63 for ; Wed, 9 Feb 2022 17:01:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 35F1B3857C63 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D9DE2ED1 for ; Wed, 9 Feb 2022 09:01:14 -0800 (PST) Received: from localhost (unknown [10.32.98.88]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6E8443F73B for ; Wed, 9 Feb 2022 09:01:14 -0800 (PST) To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [pushed 4/8] aarch64: Remove redundant vec_concat patterns References: Date: Wed, 09 Feb 2022 17:01:12 +0000 In-Reply-To: (Richard Sandiford's message of "Wed, 09 Feb 2022 17:00:03 +0000") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Sandiford via Gcc-patches From: Richard Sandiford Reply-To: Richard Sandiford Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" move_lo_quad_internal_ and move_lo_quad_internal_be_ partially duplicate the later aarch64_combinez{,_be} patterns. The duplication itself is a regression. The only substantive differences between the two are: * combinez uses vector MOV (ORR) instead of element MOV (DUP). The former seems more likely to be handled via renaming. * combinez disparages the GPR->FPR alternative whereas move_lo_quad gave it equal cost. The new test gives a token example of when the combinez behaviour helps. gcc/ * config/aarch64/aarch64-simd.md (move_lo_quad_internal_) (move_lo_quad_internal_be_): Delete. (move_lo_quad_): Use aarch64_combine instead of the above. gcc/testsuite/ * gcc.target/aarch64/vec-init-8.c: New test. --- gcc/config/aarch64/aarch64-simd.md | 37 +------------------ gcc/testsuite/gcc.target/aarch64/vec-init-8.c | 15 ++++++++ 2 files changed, 17 insertions(+), 35 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/vec-init-8.c diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index c5bc2ea658b..d6cd4c70fe7 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1584,46 +1584,13 @@ (define_insn "aarch64_p" ;; On little-endian this is { operand, zeroes } ;; On big-endian this is { zeroes, operand } -(define_insn "move_lo_quad_internal_" - [(set (match_operand:VQMOV 0 "register_operand" "=w,w,w") - (vec_concat:VQMOV - (match_operand: 1 "register_operand" "w,r,r") - (match_operand: 2 "aarch64_simd_or_scalar_imm_zero")))] - "TARGET_SIMD && !BYTES_BIG_ENDIAN" - "@ - dup\\t%d0, %1.d[0] - fmov\\t%d0, %1 - dup\\t%d0, %1" - [(set_attr "type" "neon_dup,f_mcr,neon_dup") - (set_attr "length" "4") - (set_attr "arch" "simd,fp,simd")] -) - -(define_insn "move_lo_quad_internal_be_" - [(set (match_operand:VQMOV 0 "register_operand" "=w,w,w") - (vec_concat:VQMOV - (match_operand: 2 "aarch64_simd_or_scalar_imm_zero") - (match_operand: 1 "register_operand" "w,r,r")))] - "TARGET_SIMD && BYTES_BIG_ENDIAN" - "@ - dup\\t%d0, %1.d[0] - fmov\\t%d0, %1 - dup\\t%d0, %1" - [(set_attr "type" "neon_dup,f_mcr,neon_dup") - (set_attr "length" "4") - (set_attr "arch" "simd,fp,simd")] -) - (define_expand "move_lo_quad_" [(match_operand:VQMOV 0 "register_operand") (match_operand: 1 "register_operand")] "TARGET_SIMD" { - rtx zs = CONST0_RTX (mode); - if (BYTES_BIG_ENDIAN) - emit_insn (gen_move_lo_quad_internal_be_ (operands[0], operands[1], zs)); - else - emit_insn (gen_move_lo_quad_internal_ (operands[0], operands[1], zs)); + emit_insn (gen_aarch64_combine (operands[0], operands[1], + CONST0_RTX (mode))); DONE; } ) diff --git a/gcc/testsuite/gcc.target/aarch64/vec-init-8.c b/gcc/testsuite/gcc.target/aarch64/vec-init-8.c new file mode 100644 index 00000000000..18f8afe10f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vec-init-8.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O" } */ + +#include + +int64x2_t f1(int64_t *ptr) { + int64_t x = *ptr; + asm volatile ("" ::: "memory"); + if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) + return (int64x2_t) { 0, x }; + else + return (int64x2_t) { x, 0 }; +} + +/* { dg-final { scan-assembler {\tldr\td0, \[x0\]\n} } } */