aarch64: Add ISA requirements to some SVE/SME md comments

  Kyrylo Tkachov <ktkachov@nvidia.com> writes:
> Hi Richard
>> On 6 Nov 2024, at 18:16, Richard Sandiford <richard.sandiford@arm.com> wrote:
>> 
>> This series adds support for FEAT_SVE2p1 (-march=...+sve2p1).
>> One thing that the extension does is make some SME and SME2 instructions
>> available outside of streaming mode.  It also adds quite a few new
>> instructions.  Some of those new instructions are shared with SME2.1,
>> which will be added by a later patch.
>> 
>> Tested on aarch64-linux-gnu.  GNU binutils doesn't yet have full
>> support for SVE2.1, meaning that the aarch64_asm_sve2p1_ok target
>> selector fails and that the new aarch64-sve2-acle-asm.exp tests fall
>> back to "dg-do compile" instead of "dg-do assemble".  However, I also
>> tested aarch64-sve2-acle-asm.exp against LLVM's assembler using a
>> hacked-up script.
>> 
>> I also tried to cross-check GCC's implementation against LLVM's SVE2.1
>> ACLE tests.  There were some failures due to missing B16B16 support
>> (part of a separate follow-on series) and the fact that LLVM's stores
>> take pointers to const (raised separately), but otherwise things
>> seemed ok.
>> 
>> I'll commit this on Monday if there are no comments before then,
>> but please let me know if you'd like me to wait longer.  It will
>> likely need some minor updates due to conflicts with other
>> in-flight patches.
>
> Thanks for these!
> One suggestion I have is that for the patterns in aarch64-sve2.md we may want to have SVE2p1 in the comments for the new instructions.
> For example, we have:
> ;; -------------------------------------------------------------------------
> ;; ---- [FP] Clamp to minimum/maximum
> ;; -------------------------------------------------------------------------
> ;; - BFCLAMP (SVE_B16B16)
> ;; - FCLAMP
> ;; -------------------------------------------------------------------------
> Which shows what extension is BFCLAMP a part of.
> I personally find these comments useful when quickly looking for what’s in the base architecture and what’s not and it’d be nice to keep this scheme going though I notice we’re already not totally consistent about it.
> I don’t insist on it, but it’s a suggestion.

Ah, yeah, good point.  I've applied the patch below to do that.

(And sorry for the delay.  I thought it would be fairer to wait until
Claudio's patches were in, to avoid creating more churn for that series.)

Thanks,
Richard

----

The SVE and SME md files are divided into sections, with each
section often starting with a comment that lists the associated
mnemonics.  These lists usually include the base architecture
requirement in parentheses, if the base requirement is greater
than the baseline for the file.  This patch tries to be more
consistent about when we do that for the recently added SVE2p1
and SME2p1 extensions.

gcc/
	* config/aarch64/aarch64-sme.md: In the section comments, add the
	architecture requirements alongside some mnemonics.
	* config/aarch64/aarch64-sve2.md: Likewise.
---
 gcc/config/aarch64/aarch64-sme.md  |  72 ++++++-------
 gcc/config/aarch64/aarch64-sve2.md | 162 +++++++++++++++--------------
 2 files changed, 121 insertions(+), 113 deletions(-)
  

> On 29 Nov 2024, at 13:04, Richard Sandiford <richard.sandiford@arm.com> wrote:
> 
> Kyrylo Tkachov <ktkachov@nvidia.com> writes:
>> Hi Richard
>>> On 6 Nov 2024, at 18:16, Richard Sandiford <richard.sandiford@arm.com> wrote:
>>> 
>>> This series adds support for FEAT_SVE2p1 (-march=...+sve2p1).
>>> One thing that the extension does is make some SME and SME2 instructions
>>> available outside of streaming mode.  It also adds quite a few new
>>> instructions.  Some of those new instructions are shared with SME2.1,
>>> which will be added by a later patch.
>>> 
>>> Tested on aarch64-linux-gnu.  GNU binutils doesn't yet have full
>>> support for SVE2.1, meaning that the aarch64_asm_sve2p1_ok target
>>> selector fails and that the new aarch64-sve2-acle-asm.exp tests fall
>>> back to "dg-do compile" instead of "dg-do assemble".  However, I also
>>> tested aarch64-sve2-acle-asm.exp against LLVM's assembler using a
>>> hacked-up script.
>>> 
>>> I also tried to cross-check GCC's implementation against LLVM's SVE2.1
>>> ACLE tests.  There were some failures due to missing B16B16 support
>>> (part of a separate follow-on series) and the fact that LLVM's stores
>>> take pointers to const (raised separately), but otherwise things
>>> seemed ok.
>>> 
>>> I'll commit this on Monday if there are no comments before then,
>>> but please let me know if you'd like me to wait longer.  It will
>>> likely need some minor updates due to conflicts with other
>>> in-flight patches.
>> 
>> Thanks for these!
>> One suggestion I have is that for the patterns in aarch64-sve2.md we may want to have SVE2p1 in the comments for the new instructions.
>> For example, we have:
>> ;; -------------------------------------------------------------------------
>> ;; ---- [FP] Clamp to minimum/maximum
>> ;; -------------------------------------------------------------------------
>> ;; - BFCLAMP (SVE_B16B16)
>> ;; - FCLAMP
>> ;; -------------------------------------------------------------------------
>> Which shows what extension is BFCLAMP a part of.
>> I personally find these comments useful when quickly looking for what’s in the base architecture and what’s not and it’d be nice to keep this scheme going though I notice we’re already not totally consistent about it.
>> I don’t insist on it, but it’s a suggestion.
> 
> Ah, yeah, good point.  I've applied the patch below to do that.
> 
> (And sorry for the delay.  I thought it would be fairer to wait until
> Claudio's patches were in, to avoid creating more churn for that series.)

Thanks Richard, this is very helpful.
Kyrill

> 
> Thanks,
> Richard
> 
> ----
> 
> The SVE and SME md files are divided into sections, with each
> section often starting with a comment that lists the associated
> mnemonics.  These lists usually include the base architecture
> requirement in parentheses, if the base requirement is greater
> than the baseline for the file.  This patch tries to be more
> consistent about when we do that for the recently added SVE2p1
> and SME2p1 extensions.
> 
> gcc/
> * config/aarch64/aarch64-sme.md: In the section comments, add the
> architecture requirements alongside some mnemonics.
> * config/aarch64/aarch64-sve2.md: Likewise.
> ---
> gcc/config/aarch64/aarch64-sme.md  |  72 ++++++-------
> gcc/config/aarch64/aarch64-sve2.md | 162 +++++++++++++++--------------
> 2 files changed, 121 insertions(+), 113 deletions(-)
> 
> diff --git a/gcc/config/aarch64/aarch64-sme.md b/gcc/config/aarch64/aarch64-sme.md
> index 0f362671f75..e4562186bdd 100644
> --- a/gcc/config/aarch64/aarch64-sme.md
> +++ b/gcc/config/aarch64/aarch64-sme.md
> @@ -533,7 +533,7 @@ (define_insn "@aarch64_sme_ldrn<mode>"
> ;; ---- Table loads
> ;; -------------------------------------------------------------------------
> ;; Includes:
> -;; - LDR
> +;; - LDR (SME2)
> ;; -------------------------------------------------------------------------
> 
> (define_c_enum "unspec" [
> @@ -635,7 +635,7 @@ (define_insn "@aarch64_sme_strn<mode>"
> ;; ---- Table stores
> ;; -------------------------------------------------------------------------
> ;; Includes:
> -;; - STR
> +;; - STR (SME2)
> ;; -------------------------------------------------------------------------
> 
> (define_insn "aarch64_sme_str_zt0"
> @@ -651,7 +651,7 @@ (define_insn "aarch64_sme_str_zt0"
> ;; -------------------------------------------------------------------------
> ;; Includes:
> ;; - MOVA
> -;; - MOVAZ
> +;; - MOVAZ (SME2p1)
> ;; -------------------------------------------------------------------------
> 
> (define_insn "@aarch64_sme_<optab><v_int_container><mode>"
> @@ -813,7 +813,7 @@ (define_insn "@aarch64_sme_<optab><VNx1TI_ONLY:mode><SVE_FULL:mode>"
> ;; -------------------------------------------------------------------------
> ;; Includes:
> ;; - MOVA
> -;; - MOVAZ
> +;; - MOVAZ (SME2p1)
> ;; -------------------------------------------------------------------------
> 
> (define_insn "@aarch64_sme_<optab><mode><mode>"
> @@ -1140,12 +1140,12 @@ (define_insn "@aarch64_sme_<optab><mode>"
> ;; ---- Binary arithmetic on ZA slice
> ;; -------------------------------------------------------------------------
> ;; Includes:
> -;; - ADD
> -;; - BFADD
> -;; - BFSUB
> -;; - FADD
> -;; - FSUB
> -;; - SUB
> +;; - ADD (SME2)
> +;; - BFADD (SME_B16B16)
> +;; - BFSUB (SME_B16B16)
> +;; - FADD (SME2)
> +;; - FSUB (SME2)
> +;; - SUB (SME2)
> ;; -------------------------------------------------------------------------
> 
> (define_insn "@aarch64_sme_<optab><mode>"
> @@ -1202,8 +1202,8 @@ (define_insn "*aarch64_sme_<optab><mode>_plus"
> ;; ---- Binary arithmetic, writing to ZA slice
> ;; -------------------------------------------------------------------------
> ;; Includes:
> -;; - ADD
> -;; - SUB
> +;; - ADD (SME2)
> +;; - SUB (SME2)
> ;; -------------------------------------------------------------------------
> 
> (define_insn "@aarch64_sme_<optab><mode>"
> @@ -1270,10 +1270,10 @@ (define_insn "*aarch64_sme_single_<optab><mode>_plus"
> ;; ---- [INT] Dot product
> ;; -------------------------------------------------------------------------
> ;; Includes:
> -;; - SDOT
> -;; - SUDOT
> -;; - UDOT
> -;; - USDOT
> +;; - SDOT (SME2)
> +;; - SUDOT (SME2)
> +;; - UDOT (SME2)
> +;; - USDOT (SME2)
> ;; -------------------------------------------------------------------------
> 
> (define_insn "@aarch64_sme_<optab><SME_ZA_SDI:mode><SME_ZA_BHIx24:mode>"
> @@ -1411,10 +1411,10 @@ (define_insn "*aarch64_sme_lane_<optab><SME_ZA_SDI:mode><SME_ZA_BHIx24:mode>_plu
> ;; ---- [INT] Ternary widening arithmetic on ZA slice
> ;; -------------------------------------------------------------------------
> ;; Includes:
> -;; - SMLA
> -;; - SMLS
> -;; - UMLA
> -;; - UMLS
> +;; - SMLA (SME2)
> +;; - SMLS (SME2)
> +;; - UMLA (SME2)
> +;; - UMLS (SME2)
> ;; -------------------------------------------------------------------------
> 
> (define_insn "@aarch64_sme_<optab><VNx4SI_ONLY:mode><SVE_FULL_BHI:mode>"
> @@ -1676,8 +1676,8 @@ (define_insn "*aarch64_sme_lane_<optab><VNx2DI_ONLY:mode><SME_ZA_HIx124:mode>"
> ;; -------------------------------------------------------------------------
> ;; ---- [INT] Sum of outer products
> ;; -------------------------------------------------------------------------
> -;; - BMOPA
> -;; - BMOPS
> +;; - BMOPA (SME2)
> +;; - BMOPS (SME2)
> ;; - SMOPA
> ;; - SMOPS
> ;; - SUMOPA
> @@ -1752,8 +1752,8 @@ (define_insn "@aarch64_sme_<optab><VNx4SI_ONLY:mode><VNx4SI_ONLY:mode>"
> ;; ---- [FP] Dot product
> ;; -------------------------------------------------------------------------
> ;; Includes:
> -;; - BFDOT
> -;; - FDOT
> +;; - BFDOT (SME2)
> +;; - FDOT (SME2)
> ;; -------------------------------------------------------------------------
> 
> (define_insn "@aarch64_sme_<optab><VNx4SI_ONLY:mode><SME_ZA_HFx24:mode>"
> @@ -1849,10 +1849,10 @@ (define_insn "*aarch64_sme_lane_<optab><VNx4SI_ONLY:mode><SME_ZA_HFx24:mode>_plu
> ;; ---- [FP] Ternary arithmetic on ZA slice
> ;; -------------------------------------------------------------------------
> ;; Includes:
> -;; - BFMLA
> -;; - BFMLS
> -;; - FMLA
> -;; - FMLS
> +;; - BFMLA (SME_B16B16)
> +;; - BFMLS (SME_B16B16)
> +;; - FMLA (SME2)
> +;; - FMLS (SME2)
> ;; -------------------------------------------------------------------------
> 
> (define_insn "@aarch64_sme_<optab><mode><mode>"
> @@ -1948,10 +1948,10 @@ (define_insn "*aarch64_sme_lane_<optab><mode><mode>"
> ;; ---- [FP] Ternary widening arithmetic on ZA slice
> ;; -------------------------------------------------------------------------
> ;; Includes:
> -;; - BFMLAL
> -;; - BFMLSL
> -;; - FMLAL
> -;; - FMLSL
> +;; - BFMLAL (SME2)
> +;; - BFMLSL (SME2)
> +;; - FMLAL (SME2)
> +;; - FMLSL (SME2)
> ;; -------------------------------------------------------------------------
> 
> (define_insn "@aarch64_sme_<optab><VNx4SI_ONLY:mode><SVE_FULL_HF:mode>"
> @@ -2086,8 +2086,8 @@ (define_insn "*aarch64_sme_lane_<optab><VNx4SI_ONLY:mode><SME_ZA_HFx124:mode>"
> ;; ---- [FP] Sum of outer products
> ;; -------------------------------------------------------------------------
> ;; Includes:
> -;; - BFMOPA
> -;; - BFMOPS
> +;; - BFMOPA (SME_B16B16)
> +;; - BFMOPS (SME_B16B16)
> ;; - FMOPA
> ;; - FMOPS
> ;; -------------------------------------------------------------------------
> @@ -2130,8 +2130,8 @@ (define_insn "@aarch64_sme_<optab><VNx4SI_ONLY:mode><SVE_FULL_HF:mode>"
> ;; ---- Table lookup
> ;; -------------------------------------------------------------------------
> ;; Includes:
> -;; - LUTI2
> -;; - LUTI4
> +;; - LUTI2 (SME2)
> +;; - LUTI4 (SME2)
> ;; -------------------------------------------------------------------------
> 
> (define_c_enum "unspec" [
> diff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md
> index 219e9fc1c81..d26c0c55c55 100644
> --- a/gcc/config/aarch64/aarch64-sve2.md
> +++ b/gcc/config/aarch64/aarch64-sve2.md
> @@ -142,7 +142,7 @@
> ;; ---- Predicate to vector moves
> ;; -------------------------------------------------------------------------
> ;; Includes:
> -;; - PMOV (to vector)
> +;; - PMOV (to vector) (SVE2p1)
> ;; -------------------------------------------------------------------------
> 
> (define_insn "@aarch64_pmov_to_<mode>"
> @@ -169,7 +169,7 @@ (define_insn "@aarch64_pmov_lane_to_<mode>"
> ;; ---- Vector to predicate moves
> ;; -------------------------------------------------------------------------
> ;; Includes:
> -;; - PMOV (from vector)
> +;; - PMOV (from vector) (SVE2p1)
> ;; -------------------------------------------------------------------------
> 
> (define_insn "@aarch64_pmov_from_<mode>"
> @@ -199,8 +199,8 @@ (define_insn "@aarch64_pmov_lane_from_<mode>"
> ;; ---- 128-bit extending loads
> ;; -------------------------------------------------------------------------
> ;; Includes:
> -;; - LD1W (to .Q)
> -;; - LD1D (to .Q)
> +;; - LD1W (to .Q) (SVE2p1)
> +;; - LD1D (to .Q) (SVE2p1)
> ;; -------------------------------------------------------------------------
> 
> ;; There isn't really a natural way of representing these instructions
> @@ -233,9 +233,9 @@ (define_insn "@aarch64_sve_ld1_extendq<mode>"
> ;; ---- 128-bit structure loads
> ;; -------------------------------------------------------------------------
> ;; Includes:
> -;; - LD2Q
> -;; - LD3Q
> -;; - LD4Q
> +;; - LD2Q (SVE2p1)
> +;; - LD3Q (SVE2p1)
> +;; - LD4Q (SVE2p1)
> ;; -------------------------------------------------------------------------
> 
> ;; Predicated LD[234]Q.
> @@ -330,7 +330,7 @@ (define_insn "@aarch64_<optab><mode>_strided4"
> ;; ---- 128-bit gather loads
> ;; -------------------------------------------------------------------------
> ;; Includes gather forms of:
> -;; - LD1Q
> +;; - LD1Q (SVE2p1)
> ;; -------------------------------------------------------------------------
> 
> ;; Model this as operating on the largest valid element size, which is DI.
> @@ -417,8 +417,8 @@ (define_insn_and_rewrite "@aarch64_gather_ldnt_<ANY_EXTEND:optab><SVE_FULL_SDI:m
> ;; ---- 128-bit truncating stores
> ;; -------------------------------------------------------------------------
> ;; Includes:
> -;; - ST1W (from .Q)
> -;; - ST1D (from .Q)
> +;; - ST1W (from .Q) (SVE2p1)
> +;; - ST1D (from .Q) (SVE2p1)
> ;; -------------------------------------------------------------------------
> 
> ;; See the comment above the corresponding loads for a discussion about the
> @@ -438,9 +438,9 @@ (define_insn "@aarch64_sve_st1_truncq<mode>"
> ;; ---- 128-bit structure stores
> ;; -------------------------------------------------------------------------
> ;; Includes:
> -;; - ST2Q
> -;; - ST3Q
> -;; - ST4Q
> +;; - ST2Q (SVE2p1)
> +;; - ST3Q (SVE2p1)
> +;; - ST4Q (SVE2p1)
> ;; -------------------------------------------------------------------------
> 
> ;; Predicated ST[234].
> @@ -515,7 +515,7 @@ (define_insn "@aarch64_<optab><mode>_strided4"
> ;; ---- 128-bit scatter stores
> ;; -------------------------------------------------------------------------
> ;; Includes scatter form of:
> -;; - ST1Q
> +;; - ST1Q (SVE2p1)
> ;; -------------------------------------------------------------------------
> 
> (define_insn "aarch64_scatter_st1q"
> @@ -1326,12 +1326,12 @@ (define_insn_and_rewrite "*cond_<sve_int_op><mode>_any"
> ;; ---- [FP] Non-widening bfloat16 arithmetic
> ;; -------------------------------------------------------------------------
> ;; Includes:
> -;; - BFADD
> -;; - BFMAX
> -;; - BFMAXNM
> -;; - BFMIN
> -;; - BFMINNM
> -;; - BFMUL
> +;; - BFADD (SVE_B16B16)
> +;; - BFMAX (SVE_B16B16)
> +;; - BFMAXNM (SVE_B16B16)
> +;; - BFMIN (SVE_B16B16)
> +;; - BFMINNM (SVE_B16B16)
> +;; - BFMUL (SVE_B16B16)
> ;; -------------------------------------------------------------------------
> 
> ;; Predicated B16B16 binary operations.
> @@ -1999,18 +1999,18 @@ (define_insn "*aarch64_sve2_<su>aba<mode>"
> ;; ---- [FP] Mfloat8 Multiply-and-accumulate operations
> ;; -------------------------------------------------------------------------
> ;; Includes:
> -;; - FMLALB (vectors, FP8 to FP16)
> -;; - FMLALT (vectors, FP8 to FP16)
> -;; - FMLALB (indexed, FP8 to FP16)
> -;; - FMLALT (indexed, FP8 to FP16)
> -;; - FMLALLBB (vectors)
> -;; - FMLALLBB (indexed)
> -;; - FMLALLBT (vectors)
> -;; - FMLALLBT (indexed)
> -;; - FMLALLTB (vectors)
> -;; - FMLALLTB (indexed)
> -;; - FMLALLTT (vectors)
> -;; - FMLALLTT (indexed)
> +;; - FMLALB (vectors, FP8 to FP16) (FP8FMA)
> +;; - FMLALT (vectors, FP8 to FP16) (FP8FMA)
> +;; - FMLALB (indexed, FP8 to FP16) (FP8FMA)
> +;; - FMLALT (indexed, FP8 to FP16) (FP8FMA)
> +;; - FMLALLBB (vectors) (FP8FMA)
> +;; - FMLALLBB (indexed) (FP8FMA)
> +;; - FMLALLBT (vectors) (FP8FMA)
> +;; - FMLALLBT (indexed) (FP8FMA)
> +;; - FMLALLTB (vectors) (FP8FMA)
> +;; - FMLALLTB (indexed) (FP8FMA)
> +;; - FMLALLTT (vectors) (FP8FMA)
> +;; - FMLALLTT (indexed) (FP8FMA)
> ;; -------------------------------------------------------------------------
> 
> (define_insn "@aarch64_sve_add_<sve2_fp8_fma_op_vnx8hf><mode>"
> @@ -2079,10 +2079,10 @@ (define_insn "@aarch64_sve_add_lane_<sve2_fp8_fma_op_vnx4sf><mode>"
> ;; ---- [FP] Mfloat8 dot products
> ;; -------------------------------------------------------------------------
> ;; Includes:
> -;; - FDOT (4-way, vectors)
> -;; - FDOT (4-way, indexed)
> -;; - FDOT (2-way, vectors)
> -;; - FDOT (2-way, indexed)
> +;; - FDOT (4-way, vectors) (FP8DOT4)
> +;; - FDOT (4-way, indexed) (FP8DOT4)
> +;; - FDOT (2-way, vectors) (FP8DOT2)
> +;; - FDOT (2-way, indexed) (FP8DOT2)
> ;; -------------------------------------------------------------------------
> (define_insn "@aarch64_sve_dot<mode>"
>   [(set (match_operand:SVE_FULL_HSF 0 "register_operand")
> @@ -2576,10 +2576,10 @@ (define_insn "@aarch64_sve_<sve_int_op><mode>"
> ;; ---- [INT] Multi-vector narrowing unary arithmetic
> ;; -------------------------------------------------------------------------
> ;; Includes:
> -;; - SQCVT
> -;; - SQCVTN
> -;; - UQCVT
> -;; - UQCVTN
> +;; - SQCVT (SME2)
> +;; - SQCVTN (SME2)
> +;; - UQCVT (SME2)
> +;; - UQCVTN (SME2)
> ;; -------------------------------------------------------------------------
> 
> (define_insn "@aarch64_sve_<optab><VNx16QI_ONLY:mode><VNx16SI_ONLY:mode>"
> @@ -2711,12 +2711,12 @@ (define_insn "@aarch64_sve_<sve_int_op><mode>"
> ;; ---- [INT] Multi-vector narrowing right shifts
> ;; -------------------------------------------------------------------------
> ;; Includes:
> -;; - SQRSHR
> -;; - SQRSHRN
> -;; - SQRSHRU
> -;; - SQRSHRUN
> -;; - UQRSHR
> -;; - UQRSHRN
> +;; - SQRSHR (SME2)
> +;; - SQRSHRN (SVE2p1, SME2)
> +;; - SQRSHRU (SME2)
> +;; - SQRSHRUN (SVE2p1, SME2)
> +;; - UQRSHR (SME2)
> +;; - UQRSHRN (SVE2p1, SME2)
> ;; -------------------------------------------------------------------------
> 
> (define_insn "@aarch64_sve_<sve_int_op><mode>"
> @@ -3058,14 +3058,14 @@ (define_insn "@aarch64_<optab>_lane_<mode>"
> ;; ---- [FP<-FP] Widening conversions
> ;; -------------------------------------------------------------------------
> ;; Includes:
> -;; - BF1CVT
> -;; - BF1CVTLT
> -;; - BF2CVT
> -;; - BF2CVTLT
> -;; - F1CVT
> -;; - F1CVTLT
> -;; - F2CVT
> -;; - F2CVTLT
> +;; - BF1CVT (FP8)
> +;; - BF1CVTLT (FP8)
> +;; - BF2CVT (FP8)
> +;; - BF2CVTLT (FP8)
> +;; - F1CVT (FP8)
> +;; - F1CVTLT (FP8)
> +;; - F2CVT (FP8)
> +;; - F2CVTLT (FP8)
> ;; - FCVTLT
> ;; -------------------------------------------------------------------------
> 
> @@ -3261,8 +3261,8 @@ (define_insn "@aarch64_sve2_cvtxnt<mode>"
> ;; ---- [FP<-FP] Multi-vector widening conversions
> ;; -------------------------------------------------------------------------
> ;; Includes the multi-register forms of:
> -;; - FCVT
> -;; - FCVTL
> +;; - FCVT (SME_F16F16)
> +;; - FCVTL (SME_F16F16)
> ;; -------------------------------------------------------------------------
> 
> (define_insn "extendvnx8hfvnx8sf2"
> @@ -3286,12 +3286,12 @@ (define_insn "@aarch64_sve_cvtl<mode>"
> ;; ---- [FP<-FP] Multi-vector narrowing conversions
> ;; -------------------------------------------------------------------------
> ;; Includes the multi-register forms of:
> -;; - BFCVT
> -;; - BFCVTN
> -;; - FCVT
> -;; - FCVTN
> -;; - FCVTNB
> -;; - FCVTNT
> +;; - BFCVT (SME2)
> +;; - BFCVTN (SME2)
> +;; - FCVT (SME2)
> +;; - FCVTN (SME2)
> +;; - FCVTNB (FP8)
> +;; - FCVTNT (FP8)
> ;; -------------------------------------------------------------------------
> 
> (define_insn "truncvnx8sf<mode>2"
> @@ -3345,6 +3345,10 @@ (define_insn "@aarch64_sve_cvtnt<mode>"
> ;; -------------------------------------------------------------------------
> ;; ---- [FP<-INT] Multi-vector conversions
> ;; -------------------------------------------------------------------------
> +;; Includes the multi-register forms of:
> +;; - SCVTF (SME2)
> +;; - UCVTF (SME2)
> +;; -------------------------------------------------------------------------
> 
> (define_insn "<optab><v_int_equiv><mode>2"
>   [(set (match_operand:SVE_SFx24 0 "aligned_register_operand" "=Uw<vector_count>")
> @@ -3357,6 +3361,10 @@ (define_insn "<optab><v_int_equiv><mode>2"
> ;; -------------------------------------------------------------------------
> ;; ---- [INT<-FP] Multi-vector conversions
> ;; -------------------------------------------------------------------------
> +;; Includes the multi-register forms of:
> +;; - FCVTZS (SME2)
> +;; - FCVTZU (SME2)
> +;; -------------------------------------------------------------------------
> 
> (define_insn "<optab><mode><v_int_equiv>2"
>   [(set (match_operand:<V_INT_EQUIV> 0 "aligned_register_operand" "=Uw<vector_count>")
> @@ -3629,14 +3637,14 @@ (define_insn "@aarch64_sve_while<while_optab_cmp>_c<BHSD_BITS>"
> ;; ---- [INT] Reduction to 128-bit vector
> ;; -------------------------------------------------------------------------
> ;; Includes:
> -;; - ADDQV
> -;; - ANDQV
> -;; - EORQV
> -;; - ORQV
> -;; - SMAXQV
> -;; - SMINQV
> -;; - UMAXQV
> -;; - UMINQV
> +;; - ADDQV (SVE2p1)
> +;; - ANDQV (SVE2p1)
> +;; - EORQV (SVE2p1)
> +;; - ORQV (SVE2p1)
> +;; - SMAXQV (SVE2p1)
> +;; - SMINQV (SVE2p1)
> +;; - UMAXQV (SVE2p1)
> +;; - UMINQV (SVE2p1)
> ;; -------------------------------------------------------------------------
> 
> (define_insn "@aarch64_pred_reduc_<optab>_<mode>"
> @@ -3653,11 +3661,11 @@ (define_insn "@aarch64_pred_reduc_<optab>_<mode>"
> ;; ---- [FP] Reduction to 128-bit vector
> ;; -------------------------------------------------------------------------
> ;; Includes:
> -;; - FADDQV
> -;; - FMAXNMQV
> -;; - FMAXQV
> -;; - FMINNMQV
> -;; - FMINQV
> +;; - FADDQV (SVE2p1)
> +;; - FMAXNMQV (SVE2p1)
> +;; - FMAXQV (SVE2p1)
> +;; - FMINNMQV (SVE2p1)
> +;; - FMINQV (SVE2p1)
> ;; -------------------------------------------------------------------------
> 
> (define_insn "@aarch64_pred_reduc_<optab>_<mode>"
> @@ -3716,8 +3724,8 @@ (define_insn "@cond_<optab><mode>"
> ;; ---- [INT,FP] HVLA permutes
> ;; -------------------------------------------------------------------------
> ;; Includes:
> -;; - DUPQ
> -;; - EXTQ
> +;; - DUPQ (SVE2p1)
> +;; - EXTQ (SVE2p1)
> ;; -------------------------------------------------------------------------
> 
> (define_insn "@aarch64_sve_dupq<mode>"
> -- 
> 2.25.1
>