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Thu, 28 Apr 2022 09:50:07 +0000 To: Andrea Corallo via Gcc-patches Subject: [PATCH 10/12] arm: Implement cortex-M return signing address codegen References: Date: Thu, 28 Apr 2022 11:50:04 +0200 In-Reply-To: (Andrea Corallo via Gcc-patches's message of "Thu, 28 Apr 2022 10:39:31 +0200") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/29.0.50 (gnu/linux) MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-Office365-Filtering-Correlation-Id: b2ff5741-1aef-457e-c8c6-08da28fc8181 X-MS-TrafficTypeDiagnostic: PAXPR08MB7202:EE_|AM5EUR03FT023:EE_|DB7PR08MB3227:EE_ X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: x+uB3BzkCkk1ZHEy0P/v5dmK6FmFiy60S1Evxjzs/wouV2Wo1Z5Fvh0D5qwJpz3QLgy8dlnfQ1Yjl6HA6c/OwejDmFYVMaF4RCyhUCaBSlIVhlEbUDD6qPaTvc+ZJ0e69lzZCnjheozEs6fTRyYk7pWchoilag3nc6DKYL+QWmOQL9PmT+l+gXAEzVobS1lK3MjFFQQpJCqp3JKKEiBP1IL+3Nq/FH3jxAAdAa+I1LXZbbruCf9GV2PuvRqAjU/mVr9hIA207gke8usodxIY9kmcYARPIyvavu7R3dF69tsvGwAH9U+KDPHy1n7651+24EYypk92rn2J6ItchgmOsn/4rSA64jxxxDwog6IIjMQBGI7jaS4COnM7BRp1hXM67v31FmzIM+LwdBLOjBzSByc0z0kjgylwN/Gc+7ewkwaYDZNz1zPDeAA9Dl+v4+ZDxkZXKMK0wIJCyeVfDF8MMDvP14FKxvFBOc3z0ObvCcusSZWnr8Fa2fW/zmdJnXJjTGVoIIuHV74u6ylspRdBefSYhNJxX0NNNPQvBfzclBLBPsMigT8Zxx3F+LOCRs8M/855iZswasxP1jfAyJcJLi3QwUCBnAdBGSqsoxjMnQNi+xe4gM4SL4PWmYkMBu80OylaZ8XmSJ2/s3B5Vsuoc3qpyY9RU5IBMal2BY7AS1JbMYt+cEp+hEoGpTMUsgYQtwl9h9iCXhsQc6JrbH0qaZJw7fihmfGox1ZSwCGIyoPgOXGcuz+ceucmezv5wAL2XLbu2gvFw+qYhpnckSW492yz71Drg1EszPePSI2p3czmbhQg56ihOlfWPH8/W07GfITlcOYqF5GDoFacDnzitA== X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; 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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230001)(4636009)(40470700004)(36840700001)(46966006)(235185007)(47076005)(84970400001)(86362001)(316002)(508600001)(2616005)(6916009)(54906003)(33964004)(70206006)(81166007)(70586007)(82310400005)(6666004)(40460700003)(26005)(426003)(336012)(5660300002)(4326008)(8936002)(36756003)(83380400001)(2906002)(44832011)(186003)(36860700001)(8676002); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Apr 2022 09:50:19.5045 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b2ff5741-1aef-457e-c8c6-08da28fc8181 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT023.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB7PR08MB3227 X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Andrea Corallo via Gcc-patches From: Andrea Corallo Reply-To: Andrea Corallo Cc: Richard Earnshaw , nd Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Hi all, this patch enables address return signature and verification based on Armv8.1-M Pointer Authentication [1]. To sign the return address, we use the PAC R12, LR, SP instruction upon function entry. This is signing LR using SP and storing the result in R12. R12 will be pushed into the stack. During function epilogue R12 will be popped and AUT R12, LR, SP will be used to verify that the content of LR is still valid before return. Here an example of PAC instrumented function prologue and epilogue: void foo (void); int main() { foo (); return 0; } Compiled with '-march=armv8.1-m.main -mbranch-protection=pac-ret -mthumb' translates into: main: pac ip, lr, sp push {r3, r7, ip, lr} add r7, sp, #0 bl foo movs r3, #0 mov r0, r3 pop {r3, r7, ip, lr} aut ip, lr, sp bx lr The patch also takes care of generating a PACBTI instruction in place of the sequence BTI+PAC when Branch Target Identification is enabled contextually. Ex. the previous example compiled with '-march=armv8.1-m.main -mbranch-protection=pac-ret+bti -mthumb' translates into: main: pacbti ip, lr, sp push {r3, r7, ip, lr} add r7, sp, #0 bl foo movs r3, #0 mov r0, r3 pop {r3, r7, ip, lr} aut ip, lr, sp bx lr As part of previous upstream suggestions a test for varargs has been added and '-mtpcs-frame' is deemed being incompatible with this return signing address feature being introduced. [1] gcc/Changelog * config/arm/arm.c: (arm_compute_frame_layout) (arm_expand_prologue, thumb2_expand_return, arm_expand_epilogue) (arm_conditional_register_usage): Update for pac codegen. (arm_current_function_pac_enabled_p): New function. * config/arm/arm.md (pac_ip_lr_sp, pacbti_ip_lr_sp, aut_ip_lr_sp): Add new patterns. * config/arm/unspecs.md (UNSPEC_PAC_IP_LR_SP) (UNSPEC_PACBTI_IP_LR_SP, UNSPEC_AUT_IP_LR_SP): Add unspecs. gcc/testsuite/Changelog * gcc.target/arm/pac.h : New file. * gcc.target/arm/pac-1.c : New test case. * gcc.target/arm/pac-2.c : Likewise. * gcc.target/arm/pac-3.c : Likewise. * gcc.target/arm/pac-4.c : Likewise. * gcc.target/arm/pac-5.c : Likewise. * gcc.target/arm/pac-6.c : Likewise. * gcc.target/arm/pac-7.c : Likewise. * gcc.target/arm/pac-8.c : Likewise. diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc index ceec14f84b6..c91dae292c8 100644 --- a/gcc/config/arm/arm.cc +++ b/gcc/config/arm/arm.cc @@ -302,6 +302,7 @@ static bool arm_vectorize_vec_perm_const (machine_mode, rtx, rtx, rtx, const vec_perm_indices &); static bool aarch_macro_fusion_pair_p (rtx_insn*, rtx_insn*); +static bool arm_current_function_pac_enabled_p (void); static int arm_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost, tree vectype, @@ -21139,6 +21140,14 @@ arm_compute_save_core_reg_mask (void) save_reg_mask |= arm_compute_save_reg0_reg12_mask (); + if (arm_current_function_pac_enabled_p ()) + { + if (TARGET_TPCS_FRAME + || (TARGET_TPCS_LEAF_FRAME && crtl->is_leaf)) + error ("TPCS incompatible with return address signing."); + save_reg_mask |= 1 << IP_REGNUM; + } + /* Decide if we need to save the link register. Interrupt routines have their own banked link register, so they never need to save it. @@ -22302,7 +22311,7 @@ arm_emit_multi_reg_pop (unsigned long saved_regs_mask) par = emit_insn (par); REG_NOTES (par) = dwarf; - if (!return_in_pc) + if (!return_in_pc && !frame_pointer_needed) arm_add_cfa_adjust_cfa_note (par, UNITS_PER_WORD * num_regs, stack_pointer_rtx, stack_pointer_rtx); } @@ -23352,6 +23361,11 @@ output_probe_stack_range (rtx reg1, rtx reg2) return ""; } +static bool aarch_bti_enabled () +{ + return false; +} + /* Generate the prologue instructions for entry into an ARM or Thumb-2 function. */ void @@ -23431,11 +23445,12 @@ arm_expand_prologue (void) /* The static chain register is the same as the IP register. If it is clobbered when creating the frame, we need to save and restore it. */ clobber_ip = IS_NESTED (func_type) - && ((TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM) - || ((flag_stack_check == STATIC_BUILTIN_STACK_CHECK - || flag_stack_clash_protection) - && !df_regs_ever_live_p (LR_REGNUM) - && arm_r3_live_at_start_p ())); + && (((TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM) + || ((flag_stack_check == STATIC_BUILTIN_STACK_CHECK + || flag_stack_clash_protection) + && !df_regs_ever_live_p (LR_REGNUM) + && arm_r3_live_at_start_p ())) + || (arm_current_function_pac_enabled_p ())); /* Find somewhere to store IP whilst the frame is being created. We try the following places in order: @@ -23511,6 +23526,14 @@ arm_expand_prologue (void) } } + if (arm_current_function_pac_enabled_p ()) + { + if (aarch_bti_enabled ()) + emit_insn (gen_pacbti_nop ()); + else + emit_insn (gen_pac_nop ()); + } + if (TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM) { if (IS_INTERRUPT (func_type)) @@ -27299,7 +27322,8 @@ thumb2_expand_return (bool simple_return) to assert it for now to ensure that future code changes do not silently change this behavior. */ gcc_assert (!IS_CMSE_ENTRY (arm_current_func_type ())); - if (num_regs == 1) + if (num_regs == 1 + && !(arm_current_function_pac_enabled_p ())) { rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2)); rtx reg = gen_rtx_REG (SImode, PC_REGNUM); @@ -27314,10 +27338,20 @@ thumb2_expand_return (bool simple_return) } else { - saved_regs_mask &= ~ (1 << LR_REGNUM); - saved_regs_mask |= (1 << PC_REGNUM); - arm_emit_multi_reg_pop (saved_regs_mask); - } + if (arm_current_function_pac_enabled_p ()) + { + saved_regs_mask &= ~ (1 << PC_REGNUM); + arm_emit_multi_reg_pop (saved_regs_mask); + emit_insn (gen_aut_nop ()); + emit_jump_insn (simple_return_rtx); + } + else + { + saved_regs_mask &= ~ (1 << LR_REGNUM); + saved_regs_mask |= (1 << PC_REGNUM); + arm_emit_multi_reg_pop (saved_regs_mask); + } + } } else { @@ -27723,7 +27757,8 @@ arm_expand_epilogue (bool really_return) && really_return && crtl->args.pretend_args_size == 0 && saved_regs_mask & (1 << LR_REGNUM) - && !crtl->calls_eh_return) + && !crtl->calls_eh_return + && !arm_current_function_pac_enabled_p ()) { saved_regs_mask &= ~(1 << LR_REGNUM); saved_regs_mask |= (1 << PC_REGNUM); @@ -27837,6 +27872,9 @@ arm_expand_epilogue (bool really_return) } } + if (arm_current_function_pac_enabled_p ()) + emit_insn (gen_aut_nop ()); + if (!really_return) return; @@ -30541,6 +30579,9 @@ arm_conditional_register_usage (void) global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; } + if (TARGET_HAVE_PACBTI) + call_used_regs[IP_REGNUM] = 1; + /* The Q and GE bits are only accessed via special ACLE patterns. */ CLEAR_HARD_REG_BIT (operand_reg_set, APSRQ_REGNUM); CLEAR_HARD_REG_BIT (operand_reg_set, APSRGE_REGNUM); @@ -32931,6 +32972,15 @@ arm_fusion_enabled_p (tune_params::fuse_ops op) return current_tune->fusible_ops & op; } +/* Return TRUE if return address signing mechanism is enabled. */ +static bool +arm_current_function_pac_enabled_p (void) +{ + return aarch_ra_sign_scope == AARCH_FUNCTION_ALL + || (aarch_ra_sign_scope == AARCH_FUNCTION_NON_LEAF + && !crtl->is_leaf); +} + /* Implement TARGET_SCHED_CAN_SPECULATE_INSN. Return true if INSN can be scheduled for speculative execution. Reject the long-running division and square-root instructions. */ diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 60468f6182c..b480f76a876 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -12890,6 +12890,29 @@ (set_attr "length" "8")] ) +(define_insn "pac_nop" + [(set (reg:SI IP_REGNUM) + (unspec:SI [(reg:SI SP_REGNUM) (reg:SI LR_REGNUM)] + UNSPEC_PAC_NOP))] + "TARGET_THUMB2" + "pac\t%|ip, %|lr, %|sp" + [(set_attr "length" "2")]) + +(define_insn "pacbti_nop" + [(set (reg:SI IP_REGNUM) + (unspec:SI [(reg:SI SP_REGNUM) (reg:SI LR_REGNUM)] + UNSPEC_PACBTI_NOP))] + "TARGET_THUMB2" + "pacbti\t%|ip, %|lr, %|sp" + [(set_attr "length" "2")]) + +(define_insn "aut_nop" + [(unspec:SI [(reg:SI IP_REGNUM) (reg:SI SP_REGNUM) (reg:SI LR_REGNUM)] + UNSPEC_AUT_NOP)] + "TARGET_THUMB2" + "aut\t%|ip, %|lr, %|sp" + [(set_attr "length" "2")]) + ;; Vector bits common to IWMMXT, Neon and MVE (include "vec-common.md") ;; Load the Intel Wireless Multimedia Extension patterns diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index 7748e784379..dbe243a03f6 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -159,6 +159,9 @@ UNSPEC_VCDE ; Custom Datapath Extension instruction. UNSPEC_VCDEA ; Custom Datapath Extension instruction. UNSPEC_DLS ; Used for DLS (Do Loop Start), Armv8.1-M Mainline instruction + UNSPEC_PAC_NOP ; Represents PAC signing LR + UNSPEC_PACBTI_NOP ; Represents PAC signing LR + valid landing pad + UNSPEC_AUT_NOP ; Represents PAC verifying LR ]) diff --git a/gcc/testsuite/gcc.target/arm/pac-1.c b/gcc/testsuite/gcc.target/arm/pac-1.c new file mode 100644 index 00000000000..627a93f8a56 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pac-1.c @@ -0,0 +1,9 @@ +/* Testing return address signing. */ +/* { dg-do run } */ +/* { dg-options "-march=armv8.1-m.main -mbranch-protection=pac-ret+leaf -mthumb --save-temps -O0" } */ + +#include "pac.h" + +/* { dg-final { scan-assembler-times "pac\tip, lr, sp" 2 } } */ +/* { dg-final { scan-assembler-times "aut\tip, lr, sp" 2 } } */ +/* { dg-final { scan-assembler-not "bti" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pac-2.c b/gcc/testsuite/gcc.target/arm/pac-2.c new file mode 100644 index 00000000000..a89eb73f012 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pac-2.c @@ -0,0 +1,9 @@ +/* Testing return address signing. */ +/* { dg-do run } */ +/* { dg-options "-march=armv8.1-m.main -mbranch-protection=pac-ret -mthumb --save-temps -O0" } */ + +#include "pac.h" + +/* { dg-final { scan-assembler "pac\tip, lr, sp" } } */ +/* { dg-final { scan-assembler "aut\tip, lr, sp" } } */ +/* { dg-final { scan-assembler-not "bti" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pac-3.c b/gcc/testsuite/gcc.target/arm/pac-3.c new file mode 100644 index 00000000000..a241fd0f172 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pac-3.c @@ -0,0 +1,9 @@ +/* Testing return address signing. */ +/* { dg-do run } */ +/* { dg-options "-march=armv8.1-m.main -mbranch-protection=bti+pac-ret+leaf -mthumb --save-temps -O2" } */ + +#include "pac.h" + +/* { dg-final { scan-assembler-times "pacbti\tip, lr, sp" 2 } } */ +/* { dg-final { scan-assembler-times "aut\tip, lr, sp" 2 } } */ +/* { dg-final { scan-assembler-not "\tbti\t" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pac-4.c b/gcc/testsuite/gcc.target/arm/pac-4.c new file mode 100644 index 00000000000..63dc9a9e08e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pac-4.c @@ -0,0 +1,9 @@ +/* Testing return address signing. */ +/* { dg-do compile } */ +/* { dg-options "-march=armv8.1-m.main+pacbti -mthumb --save-temps -O2" } */ + +#include "pac.h" + +/* { dg-final { scan-assembler-not "\tbti\t" } } */ +/* { dg-final { scan-assembler-not "\tpac\t" } } */ +/* { dg-final { scan-assembler-not "\tpacbti\t" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pac-5.c b/gcc/testsuite/gcc.target/arm/pac-5.c new file mode 100644 index 00000000000..97de00d8057 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pac-5.c @@ -0,0 +1,26 @@ +/* Testing return address signing. */ +/* { dg-do run } */ +/* { dg-options "-march=armv8.1-m.main -mbranch-protection=pac-ret+leaf -mthumb --save-temps -O0" } */ + +#include + +int +__attribute__((noinline)) +foo1 (int a, int b) +{ + int square (int z) { return z * z; } + return square (a) + square (b); +} + +int +main (void) +{ + if (foo1 (1, 2) != 5) + abort (); + + return 0; +} + +/* { dg-final { scan-assembler-times "pac\tip, lr, sp" 3 } } */ +/* { dg-final { scan-assembler-times "aut\tip, lr, sp" 3 } } */ +/* { dg-final { scan-assembler-not "bti" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pac-6.c b/gcc/testsuite/gcc.target/arm/pac-6.c new file mode 100644 index 00000000000..0d640751335 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pac-6.c @@ -0,0 +1,18 @@ +/* Check that GCC does .save and .cfi_offset directives with RA_AUTH_CODE pseudo hard-register. */ +/* { dg-do compile } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" "-mcpu=*" } } */ +/* { dg-options "-march=armv8.1-m.main -mbranch-protection=pac-ret+leaf -mthumb --save-temps -O0 -g" } */ + +int i; + +void foo (int); + +int bar() +{ + foo (i); + return 0; +} + +/* { dg-final { scan-assembler "pac\tip, lr, sp" } } */ +/* { dg-final { scan-assembler "aut\tip, lr, sp" } } */ +/* { dg-final { scan-assembler-not "bti" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pac-7.c b/gcc/testsuite/gcc.target/arm/pac-7.c new file mode 100644 index 00000000000..3882b05a9be --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pac-7.c @@ -0,0 +1,30 @@ +/* Testing return address signing. */ +/* { dg-do run } */ +/* { dg-options "-march=armv8.1-m.main -mbranch-protection=pac-ret+leaf -mthumb --save-temps -O0" } */ + +#include + +int +__attribute__((noinline)) +foo1 (int a, int b) +{ + int x = 4; + int foo2 (int a, int b) + { + return a + b + x; + } + return foo2 (a, b); +} + +int +main (void) +{ + if (foo1 (1, 2) != 7) + abort (); + + return 0; +} + +/* { dg-final { scan-assembler-times "pac\tip, lr, sp" 3 } } */ +/* { dg-final { scan-assembler-times "aut\tip, lr, sp" 3 } } */ +/* { dg-final { scan-assembler-not "bti" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pac-8.c b/gcc/testsuite/gcc.target/arm/pac-8.c new file mode 100644 index 00000000000..35728308c32 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pac-8.c @@ -0,0 +1,32 @@ +/* Testing return address signing. */ +/* { dg-do run } */ +/* { dg-options "-march=armv8.1-m.main -mbranch-protection=pac-ret+leaf -mthumb --save-temps -O0" } */ + +#include +#include + +int acc (int n, ...) +{ + int sum = 0; + va_list ptr; + + va_start (ptr, n); + + for (int i = 0; i < n; i++) + sum += va_arg (ptr, int); + va_end (ptr); + + return sum; +} + +int main() +{ + if (acc (3, 1, 2, 3) != 6) + abort (); + + return 0; +} + +/* { dg-final { scan-assembler-times "pac\tip, lr, sp" 2 } } */ +/* { dg-final { scan-assembler-times "aut\tip, lr, sp" 2 } } */ +/* { dg-final { scan-assembler-not "bti" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pac.h b/gcc/testsuite/gcc.target/arm/pac.h new file mode 100644 index 00000000000..7355e6b2954 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pac.h @@ -0,0 +1,17 @@ +#include + +int +__attribute__((noinline)) +foo1 (int a, int b) +{ + return a + b; +} + +int +main (void) +{ + if (foo1 (1, 2) != 3) + abort (); + + return 0; +}