From patchwork Thu Jan 11 09:54:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: joshua X-Patchwork-Id: 83870 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2454A3857038 for ; Thu, 11 Jan 2024 09:55:39 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from out30-133.freemail.mail.aliyun.com (out30-133.freemail.mail.aliyun.com [115.124.30.133]) by sourceware.org (Postfix) with ESMTPS id 8F4893857BAA for ; Thu, 11 Jan 2024 09:54:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8F4893857BAA Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.alibaba.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 8F4893857BAA Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=115.124.30.133 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704966895; cv=none; b=YZU5tAwzLMreLhq/OzU3DBB93/YsosLVGnIA7wdQO+4U1C2xQQ8QeODgNjOKotkJdMTZrDcoYxThhtVQOvyBIb5xF8qjbVtJUHRsCaxnMb/YsayXh2BpsR7SEfI9J3I6qb3wfYNwskFgku9HdzPXEw4CGD1n9ZrYJCQWNbZeej8= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704966895; c=relaxed/simple; bh=ry35Y0m5XBG41IXDuWT1lNlqMgQDltDChlYGm72sqfk=; h=Date:From:To:Message-ID:Subject:MIME-Version; b=TOM6Av5ZjXZUi61FM2pEuWWmVEqs7Gm5hbjt0Cco3R5Ifey+Kpt/LuI0JKRTiG+s9++1X8PyeHfJe7w+wss15q1y4iJkFAdPtzsCjzfy/sFyoZYJ6zIt0xkdC7XTpEo6ebnolyE+YwafZIrDgVz6cc9qaghaQVdkjtA63i6ZlKs= ARC-Authentication-Results: i=1; server2.sourceware.org X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R831e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018045170; MF=cooper.joshua@linux.alibaba.com; NM=1; PH=DW; RN=10; SR=0; TI=W4_0.2.3_v5ForWebDing_2125303E_1704966849271_o7001c13u; Received: from WS-web (cooper.joshua@linux.alibaba.com[W4_0.2.3_v5ForWebDing_2125303E_1704966849271_o7001c13u]) at Thu, 11 Jan 2024 17:54:09 +0800 Date: Thu, 11 Jan 2024 17:54:09 +0800 From: "joshua" To: "juzhe.zhong@rivai.ai" , "gcc-patches" Cc: "Jim Wilson" , "palmer" , "andrew" , "philipp.tomsich" , "jeffreyalaw" , "christoph.muellner" , "jinma" , "cooper.qu" Message-ID: Subject: =?utf-8?q?Re=EF=BC=9A=5BPATCH_v5=5D_RISC-V=3A_Add_support_for_xthea?= =?utf-8?q?dvector-specific_intrinsics=2E?= X-Mailer: [Alimail-Mailagent revision 79][W4_0.2.3][v5ForWebDing][Chrome] MIME-Version: 1.0 x-aliyun-im-through: {"mailThroughImNew":true} References: <7F92468914239FA8+202401111707330397793@rivai.ai> x-aliyun-mail-creator: W4_0.2.3_v5ForWebDing_SFRTW96aWxsYS81LjAgKFdpbmRvd3MgTlQgMTAuMDsgV2luNjQ7IHg2NCkgQXBwbGVXZWJLaXQvNTM3LjM2IChLSFRNTCwgbGlrZSBHZWNrbykgQ2hyb21lLzEyMC4wLjAuMCBTYWZhcmkvNTM3LjM2IEVkZy8xMjAuMC4wLjA=Ch In-Reply-To: <7F92468914239FA8+202401111707330397793@rivai.ai> X-Spam-Status: No, score=-18.8 required=5.0 tests=BAYES_00, BODY_8BITS, ENV_AND_HDR_SPF_MATCH, GIT_PATCH_0, HTML_MESSAGE, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: joshua Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org The "Add support for xtheadvector-specific intrinsics" patch has been updated according to the comments. [PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics. (gnu.org) ------------------------------------------------------------------ 发件人：juzhe.zhong@rivai.ai 发送时间：2024年1月11日(星期四) 17:07 收件人："cooper.joshua"; "gcc-patches" 抄　送：Jim Wilson; palmer; andrew; "philipp.tomsich"; jeffreyalaw; "christoph.muellner"; "cooper.joshua"; jinma; "cooper.qu" 主　题：Re: [PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics. enum required_ext { VECTOR_EXT, /* Vector extension */ + XTHEADVECTOR_EXT, /* XTheadVector extension */ ZVBB_EXT, /* Cryto vector Zvbb sub-ext */ ZVBB_OR_ZVKB_EXT, /* Cryto vector Zvbb or zvkb sub-ext */ ZVBC_EXT, /* Crypto vector Zvbc sub-ext */ Add theadvector to the end of the enum. + case XTHEADVECTOR_EXT: + return TARGET_XTHEADVECTOR; Same. + "&& register_operand (operands[0], mode) + && register_operand (operands[3], mode) + && satisfies_constraint_vu (operands[2]) + && INTVAL (operands[7]) == riscv_vector::VLMAX" You can use whole_reg_to_reg_move_p Btw, I review again : RISC-V: Handle differences between XTheadvector and Vector (any_extend:VWEXTI (match_operand: 3 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr")) (match_operand:VWEXTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && !TARGET_XTHEADVECTOR" "vext.vf2\t%0,%3%p1" [(set_attr "type" "vext") (set_attr "mode" "") @@ -3713,7 +3744,7 @@ (any_extend:VQEXTI (match_operand: 3 "register_operand" "W43,W43,W43,W43,W86,W86,W86,W86, vr, vr")) (match_operand:VQEXTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && !TARGET_XTHEADVECTOR" "vext.vf4\t%0,%3%p1" [(set_attr "type" "vext") (set_attr "mode" "") @@ -3734,7 +3765,7 @@ (any_extend:VOEXTI (match_operand: 3 "register_operand" "W87,W87,W87,W87, vr, vr")) (match_operand:VOEXTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && !TARGET_XTHEADVECTOR" "vext.vf8\t%0,%3%p1" [(set_attr "type" "vext") (set_attr "mode" "") Why do you add these !TARGERT_XTHEADVECRTOR ? juzhe.zhong@rivai.ai From: Jun Sha (Joshua) Date: 2024-01-11 16:46 To: gcc-patches CC: jim.wilson.gcc ; palmer ; andrew ; philipp.tomsich ; jeffreyalaw ; christoph.muellner ; juzhe.zhong ; Jun Sha (Joshua) ; Jin Ma ; Xianmiao Qu Subject: [PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics. This patch only involves the generation of xtheadvector special load/store instructions and vext instructions. gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class th_loadstore_width): Define new builtin bases. (class th_extract): Define new builtin bases. (BASE): Define new builtin bases. * config/riscv/riscv-vector-builtins-bases.h: Define new builtin class. * config/riscv/riscv-vector-builtins-shapes.cc (struct th_loadstore_width_def): Define new builtin shapes. (struct th_indexed_loadstore_width_def): Define new builtin shapes. (struct th_extract_def): Define new builtin shapes. (SHAPE): Define new builtin shapes. * config/riscv/riscv-vector-builtins-shapes.h: Define new builtin shapes. * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION): * config/riscv/riscv-vector-builtins.h (enum required_ext): (struct function_group_info): * config/riscv/t-riscv: Add thead-vector-builtins-functions.def * config/riscv/thead-vector.md (@pred_mov_width): Add new patterns. (*pred_mov_width): Likewise. (@pred_store_width): Likewise. (@pred_strided_load_width): Likewise. (@pred_strided_store_width): Likewise. (@pred_indexed_load_width): Likewise. (@pred_indexed_store_width): (@pred_th_extract): Likewise. (*pred_th_extract): Likewise. * config/riscv/thead-vector-builtins-functions.def: New file. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c: New test. * gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c: New test. * gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c: New test. * gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c: New test. * gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c: New test. * gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c: New test. Co-authored-by: Jin Ma Co-authored-by: Xianmiao Qu Co-authored-by: Christoph Müllner --- .../riscv/riscv-vector-builtins-bases.cc | 139 ++++++++++ .../riscv/riscv-vector-builtins-bases.h | 31 +++ .../riscv/riscv-vector-builtins-shapes.cc | 160 +++++++++++ .../riscv/riscv-vector-builtins-shapes.h | 3 + gcc/config/riscv/riscv-vector-builtins.cc | 70 +++++ gcc/config/riscv/riscv-vector-builtins.h | 3 + gcc/config/riscv/t-riscv | 1 + .../riscv/thead-vector-builtins-functions.def | 39 +++ gcc/config/riscv/thead-vector.md | 253 ++++++++++++++++++ .../riscv/rvv/xtheadvector/vlb-vsb.c | 68 +++++ .../riscv/rvv/xtheadvector/vlbu-vsb.c | 68 +++++ .../riscv/rvv/xtheadvector/vlh-vsh.c | 68 +++++ .../riscv/rvv/xtheadvector/vlhu-vsh.c | 68 +++++ .../riscv/rvv/xtheadvector/vlw-vsw.c | 68 +++++ .../riscv/rvv/xtheadvector/vlwu-vsw.c | 68 +++++ 15 files changed, 1107 insertions(+) create mode 100644 gcc/config/riscv/thead-vector-builtins-functions.def create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 46f1a1da33e..3eba7943757 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -2125,6 +2125,83 @@ public: } }; +/* Implements + * th.vl(b/h/w)[u].v/th.vs(b/h/w)[u].v/th.vls(b/h/w)[u].v/th.vss(b/h/w)[u].v/ + * th.vlx(b/h/w)[u].v/th.vs[u]x(b/h/w).v + * codegen. */ +template +class th_loadstore_width : public function_base +{ +public: + bool apply_tail_policy_p () const override { return !STORE_P; } + bool apply_mask_policy_p () const override { return !STORE_P; } + + unsigned int call_properties (const function_instance &) const override + { + if (STORE_P) + return CP_WRITE_MEMORY; + else + return CP_READ_MEMORY; + } + + bool can_be_overloaded_p (enum predication_type_index pred) const override + { + if (STORE_P || LST_TYPE == LST_INDEXED) + return true; + return pred != PRED_TYPE_none; + } + + rtx expand (function_expander &e) const override + { + gcc_assert (TARGET_XTHEADVECTOR); + if (LST_TYPE == LST_INDEXED) + { + if (STORE_P) + return e.use_exact_insn ( + code_for_pred_indexed_store_width (UNSPEC, UNSPEC, + e.vector_mode ())); + else + return e.use_exact_insn ( + code_for_pred_indexed_load_width (UNSPEC, e.vector_mode ())); + } + else if (LST_TYPE == LST_STRIDED) + { + if (STORE_P) + return e.use_contiguous_store_insn ( + code_for_pred_strided_store_width (UNSPEC, e.vector_mode ())); + else + return e.use_contiguous_load_insn ( + code_for_pred_strided_load_width (UNSPEC, e.vector_mode ())); + } + else + { + if (STORE_P) + return e.use_contiguous_store_insn ( + code_for_pred_store_width (UNSPEC, e.vector_mode ())); + else + return e.use_contiguous_load_insn ( + code_for_pred_mov_width (UNSPEC, e.vector_mode ())); + } + } +}; + +/* Implements vext.x.v. */ +class th_extract : public function_base +{ +public: + bool apply_vl_p () const override { return false; } + bool apply_tail_policy_p () const override { return false; } + bool apply_mask_policy_p () const override { return false; } + bool use_mask_predication_p () const override { return false; } + bool has_merge_operand_p () const override { return false; } + + rtx expand (function_expander &e) const override + { + gcc_assert (TARGET_XTHEADVECTOR); + return e.use_exact_insn (code_for_pred_th_extract (e.vector_mode ())); + } +}; + /* Below implements are vector crypto */ /* Implements vandn.[vv,vx] */ class vandn : public function_base @@ -2587,6 +2664,37 @@ static CONSTEXPR const seg_indexed_load vloxseg_obj; static CONSTEXPR const seg_indexed_store vsuxseg_obj; static CONSTEXPR const seg_indexed_store vsoxseg_obj; static CONSTEXPR const vlsegff vlsegff_obj; +static CONSTEXPR const th_loadstore_width vlb_obj; +static CONSTEXPR const th_loadstore_width vlbu_obj; +static CONSTEXPR const th_loadstore_width vlh_obj; +static CONSTEXPR const th_loadstore_width vlhu_obj; +static CONSTEXPR const th_loadstore_width vlw_obj; +static CONSTEXPR const th_loadstore_width vlwu_obj; +static CONSTEXPR const th_loadstore_width vsb_obj; +static CONSTEXPR const th_loadstore_width vsh_obj; +static CONSTEXPR const th_loadstore_width vsw_obj; +static CONSTEXPR const th_loadstore_width vlsb_obj; +static CONSTEXPR const th_loadstore_width vlsbu_obj; +static CONSTEXPR const th_loadstore_width vlsh_obj; +static CONSTEXPR const th_loadstore_width vlshu_obj; +static CONSTEXPR const th_loadstore_width vlsw_obj; +static CONSTEXPR const th_loadstore_width vlswu_obj; +static CONSTEXPR const th_loadstore_width vssb_obj; +static CONSTEXPR const th_loadstore_width vssh_obj; +static CONSTEXPR const th_loadstore_width vssw_obj; +static CONSTEXPR const th_loadstore_width vlxb_obj; +static CONSTEXPR const th_loadstore_width vlxbu_obj; +static CONSTEXPR const th_loadstore_width vlxh_obj; +static CONSTEXPR const th_loadstore_width vlxhu_obj; +static CONSTEXPR const th_loadstore_width vlxw_obj; +static CONSTEXPR const th_loadstore_width vlxwu_obj; +static CONSTEXPR const th_loadstore_width vsxb_obj; +static CONSTEXPR const th_loadstore_width vsxh_obj; +static CONSTEXPR const th_loadstore_width vsxw_obj; +static CONSTEXPR const th_loadstore_width vsuxb_obj; +static CONSTEXPR const th_loadstore_width vsuxh_obj; +static CONSTEXPR const th_loadstore_width vsuxw_obj; +static CONSTEXPR const th_extract vext_x_v_obj; /* Crypto Vector */ static CONSTEXPR const vandn vandn_obj; @@ -2878,6 +2986,37 @@ BASE (vloxseg) BASE (vsuxseg) BASE (vsoxseg) BASE (vlsegff) +BASE (vlb) +BASE (vlh) +BASE (vlw) +BASE (vlbu) +BASE (vlhu) +BASE (vlwu) +BASE (vsb) +BASE (vsh) +BASE (vsw) +BASE (vlsb) +BASE (vlsh) +BASE (vlsw) +BASE (vlsbu) +BASE (vlshu) +BASE (vlswu) +BASE (vssb) +BASE (vssh) +BASE (vssw) +BASE (vlxb) +BASE (vlxh) +BASE (vlxw) +BASE (vlxbu) +BASE (vlxhu) +BASE (vlxwu) +BASE (vsxb) +BASE (vsxh) +BASE (vsxw) +BASE (vsuxb) +BASE (vsuxh) +BASE (vsuxw) +BASE (vext_x_v) /* Crypto vector */ BASE (vandn) BASE (vbrev) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index 1122e3801a7..565a0311d2b 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -299,6 +299,37 @@ extern const function_base *const vloxseg; extern const function_base *const vsuxseg; extern const function_base *const vsoxseg; extern const function_base *const vlsegff; +extern const function_base *const vlb; +extern const function_base *const vlh; +extern const function_base *const vlw; +extern const function_base *const vlbu; +extern const function_base *const vlhu; +extern const function_base *const vlwu; +extern const function_base *const vsb; +extern const function_base *const vsh; +extern const function_base *const vsw; +extern const function_base *const vlsb; +extern const function_base *const vlsh; +extern const function_base *const vlsw; +extern const function_base *const vlsbu; +extern const function_base *const vlshu; +extern const function_base *const vlswu; +extern const function_base *const vssb; +extern const function_base *const vssh; +extern const function_base *const vssw; +extern const function_base *const vlxb; +extern const function_base *const vlxh; +extern const function_base *const vlxw; +extern const function_base *const vlxbu; +extern const function_base *const vlxhu; +extern const function_base *const vlxwu; +extern const function_base *const vsxb; +extern const function_base *const vsxh; +extern const function_base *const vsxw; +extern const function_base *const vsuxb; +extern const function_base *const vsuxh; +extern const function_base *const vsuxw; +extern const function_base *const vext_x_v; /* Below function_base are Vectro Crypto*/ extern const function_base *const vandn; extern const function_base *const vbrev; diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc b/gcc/config/riscv/riscv-vector-builtins-shapes.cc index 1e4f4d53de6..8e90b17a94b 100644 --- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc +++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc @@ -211,6 +211,146 @@ struct indexed_loadstore_def : public function_shape } }; +/* Add one function instance for GROUP, using operand suffix at index OI, + mode suffix at index PAIR && bi and predication suffix at index pred_idx. */ +static void +build_th_loadstore (function_builder &b, const function_group_info &group, + unsigned int pred_idx, unsigned int vec_type_idx) +{ + auto_vec argument_types; + function_instance function_instance (group.base_name, *group.base, + *group.shape, + group.ops_infos.types[vec_type_idx], + group.preds[pred_idx], &group.ops_infos); + tree return_type = group.ops_infos.ret.get_tree_type ( + group.ops_infos.types[vec_type_idx].index); + b.allocate_argument_types (function_instance, argument_types); + b.apply_predication (function_instance, return_type, argument_types); + + if (TARGET_XTHEADVECTOR && !check_type (return_type, argument_types)) + return; + + tree type = builtin_types[group.ops_infos.types[vec_type_idx].index].vector; + if (strstr (group.base_name, "l") + && strstr (group.base_name, "u") + && !TYPE_UNSIGNED (TREE_TYPE (type))) + return; + + if (strstr (group.base_name, "l") + && !strstr (group.base_name, "u") + && TYPE_UNSIGNED (TREE_TYPE (type))) + return; + + machine_mode mode = TYPE_MODE (type); + int sew = GET_MODE_BITSIZE (GET_MODE_INNER (mode)); + if (strstr (group.base_name, "h") && sew == 8) + return; + + if (strstr (group.base_name, "w") && (sew == 8 || sew ==16)) + return; + + b.add_overloaded_function (function_instance, *group.shape); + b.add_unique_function (function_instance, (*group.shape), return_type, + argument_types); +} + +/* th_loadstore_width_def class. */ +struct th_loadstore_width_def : public build_base +{ + void build (function_builder &b, + const function_group_info &group) const override + { + for (unsigned int pred_idx = 0; group.preds[pred_idx] != NUM_PRED_TYPES; + ++pred_idx) + { + for (unsigned int vec_type_idx = 0; + group.ops_infos.types[vec_type_idx].index != NUM_VECTOR_TYPES; + ++vec_type_idx) + { + build_th_loadstore (b, group, pred_idx, vec_type_idx); + } + } + } + + char *get_name (function_builder &b, const function_instance &instance, + bool overloaded_p) const override + { + /* Return nullptr if it can not be overloaded. */ + if (overloaded_p && !instance.base->can_be_overloaded_p (instance.pred)) + return nullptr; + + b.append_name ("__riscv_th_"); + b.append_name (instance.base_name); + + /* vop_v --> vop_v_. */ + if (!overloaded_p) + { + /* vop --> vop_v. */ + b.append_name (operand_suffixes[instance.op_info->op]); + /* vop_v --> vop_v_. */ + b.append_name (type_suffixes[instance.type.index].vector); + } + + /* According to rvv-intrinsic-doc, it does not add "_m" suffix + for vop_m C++ overloaded API. */ + if (overloaded_p && instance.pred == PRED_TYPE_m) + return b.finish_name (); + b.append_name (predication_suffixes[instance.pred]); + return b.finish_name (); + } +}; + + +/* th_indexed_loadstore_width_def class. */ +struct th_indexed_loadstore_width_def : public function_shape +{ + void build (function_builder &b, + const function_group_info &group) const override + { + for (unsigned int pred_idx = 0; group.preds[pred_idx] != NUM_PRED_TYPES; + ++pred_idx) + { + for (unsigned int vec_type_idx = 0; + group.ops_infos.types[vec_type_idx].index != NUM_VECTOR_TYPES; + ++vec_type_idx) + { + tree index_type = group.ops_infos.args[1].get_tree_type ( + group.ops_infos.types[vec_type_idx].index); + if (!index_type) + continue; + build_th_loadstore (b, group, pred_idx, vec_type_idx); + } + } + } + + char *get_name (function_builder &b, const function_instance &instance, + bool overloaded_p) const override + { + + /* Return nullptr if it can not be overloaded. */ + if (overloaded_p && !instance.base->can_be_overloaded_p (instance.pred)) + return nullptr; + + b.append_name ("__riscv_th_"); + b.append_name (instance.base_name); + /* vop_v --> vop_v_. */ + if (!overloaded_p) + { + /* vop --> vop_v. */ + b.append_name (operand_suffixes[instance.op_info->op]); + /* vop_v --> vop_v_. */ + b.append_name (type_suffixes[instance.type.index].vector); + } + + /* According to rvv-intrinsic-doc, it does not add "_m" suffix + for vop_m C++ overloaded API. */ + if (overloaded_p && instance.pred == PRED_TYPE_m) + return b.finish_name (); + b.append_name (predication_suffixes[instance.pred]); + return b.finish_name (); + } +}; + /* alu_def class. */ struct alu_def : public build_base { @@ -632,6 +772,23 @@ struct reduc_alu_def : public build_base } }; +/* th_extract_def class. */ +struct th_extract_def : public build_base +{ + char *get_name (function_builder &b, const function_instance &instance, + bool overloaded_p) const override + { + b.append_name ("__riscv_th_"); + b.append_name (instance.base_name); + + if (overloaded_p) + return b.finish_name (); + b.append_name (type_suffixes[instance.type.index].vector); + b.append_name (type_suffixes[instance.type.index].scalar); + return b.finish_name (); + } +}; + /* scalar_move_def class. */ struct scalar_move_def : public build_base { @@ -1094,6 +1251,8 @@ SHAPE(vsetvl, vsetvl) SHAPE(vsetvl, vsetvlmax) SHAPE(loadstore, loadstore) SHAPE(indexed_loadstore, indexed_loadstore) +SHAPE(th_loadstore_width, th_loadstore_width) +SHAPE(th_indexed_loadstore_width, th_indexed_loadstore_width) SHAPE(alu, alu) SHAPE(alu_frm, alu_frm) SHAPE(widen_alu, widen_alu) @@ -1106,6 +1265,7 @@ SHAPE(move, move) SHAPE(mask_alu, mask_alu) SHAPE(reduc_alu, reduc_alu) SHAPE(reduc_alu_frm, reduc_alu_frm) +SHAPE(th_extract, th_extract) SHAPE(scalar_move, scalar_move) SHAPE(vundefined, vundefined) SHAPE(misc, misc) diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.h b/gcc/config/riscv/riscv-vector-builtins-shapes.h index ac2a28ce017..a7624d0fabd 100644 --- a/gcc/config/riscv/riscv-vector-builtins-shapes.h +++ b/gcc/config/riscv/riscv-vector-builtins-shapes.h @@ -28,6 +28,8 @@ extern const function_shape *const vsetvl; extern const function_shape *const vsetvlmax; extern const function_shape *const loadstore; extern const function_shape *const indexed_loadstore; +extern const function_shape *const th_loadstore_width; +extern const function_shape *const th_indexed_loadstore_width; extern const function_shape *const alu; extern const function_shape *const alu_frm; extern const function_shape *const widen_alu; @@ -41,6 +43,7 @@ extern const function_shape *const mask_alu; extern const function_shape *const reduc_alu; extern const function_shape *const reduc_alu_frm; extern const function_shape *const scalar_move; +extern const function_shape *const th_extract; extern const function_shape *const vundefined; extern const function_shape *const misc; extern const function_shape *const vset; diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index 25e0b6e56de..44b9fec1898 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -934,6 +934,32 @@ static CONSTEXPR const rvv_arg_type_info ext_vcreate_args[] = {rvv_arg_type_info (RVV_BASE_vector), rvv_arg_type_info_end}; +/* A list of args for vector_type func (const scalar_type *, size_t) + * function. */ +static CONSTEXPR const rvv_arg_type_info scalar_const_ptr_size_args[] + = {rvv_arg_type_info (RVV_BASE_scalar_const_ptr), + rvv_arg_type_info (RVV_BASE_size), rvv_arg_type_info_end}; + +/* A list of args for vector_type func (const scalar_type *, eew8_index_type) + * function. */ +static CONSTEXPR const rvv_arg_type_info scalar_const_ptr_index_args[] + = {rvv_arg_type_info (RVV_BASE_scalar_const_ptr), + rvv_arg_type_info (RVV_BASE_unsigned_vector), rvv_arg_type_info_end}; + +/* A list of args for void func (scalar_type *, eew8_index_type, vector_type) + * function. */ +static CONSTEXPR const rvv_arg_type_info scalar_ptr_index_args[] + = {rvv_arg_type_info (RVV_BASE_scalar_ptr), + rvv_arg_type_info (RVV_BASE_unsigned_vector), + rvv_arg_type_info (RVV_BASE_vector), rvv_arg_type_info_end}; + +/* A list of args for void func (scalar_type *, size_t, vector_type) + * function. */ +static CONSTEXPR const rvv_arg_type_info scalar_ptr_size_args[] + = {rvv_arg_type_info (RVV_BASE_scalar_ptr), + rvv_arg_type_info (RVV_BASE_size), rvv_arg_type_info (RVV_BASE_vector), + rvv_arg_type_info_end}; + /* A list of none preds that will be registered for intrinsic functions. */ static CONSTEXPR const predication_type_index none_preds[] = {PRED_TYPE_none, NUM_PRED_TYPES}; @@ -1455,6 +1481,14 @@ static CONSTEXPR const rvv_op_info iu_shift_vvv_ops rvv_arg_type_info (RVV_BASE_vector), /* Return type */ shift_vv_args /* Args */}; +/* A static operand information for scalar_type func (vector_type, size_t) + * function registration. */ +static CONSTEXPR const rvv_op_info iu_x_s_u_ops + = {iu_ops, /* Types */ + OP_TYPE_vx, /* Suffix */ + rvv_arg_type_info (RVV_BASE_scalar), /* Return type */ + v_size_args /* Args */}; + /* A static operand information for vector_type func (vector_type, size_t) * function registration. */ static CONSTEXPR const rvv_op_info iu_shift_vvx_ops @@ -2638,6 +2672,38 @@ static CONSTEXPR const rvv_op_info all_v_vcreate_lmul4_x2_ops rvv_arg_type_info (RVV_BASE_vlmul_ext_x2), /* Return type */ ext_vcreate_args /* Args */}; +/* A static operand information for vector_type func (const scalar_type *, + * size_t) function registration. */ +static CONSTEXPR const rvv_op_info all_v_scalar_const_ptr_size_ops + = {all_ops, /* Types */ + OP_TYPE_v, /* Suffix */ + rvv_arg_type_info (RVV_BASE_vector), /* Return type */ + scalar_const_ptr_size_args /* Args */}; + +/* A static operand information for void func (scalar_type *, size_t, + * vector_type) function registration. */ +static CONSTEXPR const rvv_op_info all_v_scalar_ptr_size_ops + = {all_ops, /* Types */ + OP_TYPE_v, /* Suffix */ + rvv_arg_type_info (RVV_BASE_void), /* Return type */ + scalar_ptr_size_args /* Args */}; + +/* A static operand information for vector_type func (const scalar_type *, + * index_type) function registration. */ +static CONSTEXPR const rvv_op_info all_v_scalar_const_ptr_index_ops + = {all_ops, /* Types */ + OP_TYPE_v, /* Suffix */ + rvv_arg_type_info (RVV_BASE_vector), /* Return type */ + scalar_const_ptr_index_args /* Args */}; + +/* A static operand information for void func (scalar_type *, index_type, + * vector_type) function registration. */ +static CONSTEXPR const rvv_op_info all_v_scalar_ptr_index_ops + = {all_ops, /* Types */ + OP_TYPE_v, /* Suffix */ + rvv_arg_type_info (RVV_BASE_void), /* Return type */ + scalar_ptr_index_args /* Args */}; + /* A static operand information for vector_type func (vector_type). Some ins just supports SEW=32, such as crypto vectol Zvkg extension. * function registration. */ @@ -2816,6 +2882,10 @@ static function_group_info function_groups[] = { #define DEF_RVV_FUNCTION(NAME, SHAPE, PREDS, OPS_INFO) \ {#NAME, &bases::NAME, &shapes::SHAPE, PREDS, OPS_INFO, REQUIRED_EXTENSIONS}, #include "riscv-vector-builtins-functions.def" +#undef DEF_RVV_FUNCTION +#define DEF_RVV_FUNCTION(NAME, SHAPE, PREDS, OPS_INFO) \ + {#NAME, &bases::NAME, &shapes::SHAPE, PREDS, OPS_INFO, REQUIRED_EXTENSIONS}, +#include "thead-vector-builtins-functions.def" }; /* The RVV types, with their built-in diff --git a/gcc/config/riscv/riscv-vector-builtins.h b/gcc/config/riscv/riscv-vector-builtins.h index 54c8824ff92..a8ee39a3cb2 100644 --- a/gcc/config/riscv/riscv-vector-builtins.h +++ b/gcc/config/riscv/riscv-vector-builtins.h @@ -114,6 +114,7 @@ static const unsigned int CP_WRITE_CSR = 1U << 5; enum required_ext { VECTOR_EXT, /* Vector extension */ + XTHEADVECTOR_EXT, /* XTheadVector extension */ ZVBB_EXT, /* Cryto vector Zvbb sub-ext */ ZVBB_OR_ZVKB_EXT, /* Cryto vector Zvbb or zvkb sub-ext */ ZVBC_EXT, /* Crypto vector Zvbc sub-ext */ @@ -234,6 +235,8 @@ struct function_group_info { case VECTOR_EXT: return TARGET_VECTOR; + case XTHEADVECTOR_EXT: + return TARGET_XTHEADVECTOR; case ZVBB_EXT: return TARGET_ZVBB; case ZVBB_OR_ZVKB_EXT: diff --git a/gcc/config/riscv/t-riscv b/gcc/config/riscv/t-riscv index 32de6b851c1..38494320d8b 100644 --- a/gcc/config/riscv/t-riscv +++ b/gcc/config/riscv/t-riscv @@ -1,6 +1,7 @@ RISCV_BUILTINS_H = $(srcdir)/config/riscv/riscv-vector-builtins.h \ $(srcdir)/config/riscv/riscv-vector-builtins.def \ $(srcdir)/config/riscv/riscv-vector-builtins-functions.def \ + $(srcdir)/config/riscv/thead-vector-builtins-functions.def \ riscv-vector-type-indexer.gen.def riscv-builtins.o: $(srcdir)/config/riscv/riscv-builtins.cc $(CONFIG_H) \ diff --git a/gcc/config/riscv/thead-vector-builtins-functions.def b/gcc/config/riscv/thead-vector-builtins-functions.def new file mode 100644 index 00000000000..fd3ba29bae9 --- /dev/null +++ b/gcc/config/riscv/thead-vector-builtins-functions.def @@ -0,0 +1,39 @@ +#ifndef DEF_RVV_FUNCTION +#define DEF_RVV_FUNCTION(NAME, SHAPE, PREDS, OPS_INFO) +#endif + +#define REQUIRED_EXTENSIONS XTHEADVECTOR_EXT +DEF_RVV_FUNCTION (vlb, th_loadstore_width, full_preds, all_v_scalar_const_ptr_ops) +DEF_RVV_FUNCTION (vlh, th_loadstore_width, full_preds, all_v_scalar_const_ptr_ops) +DEF_RVV_FUNCTION (vlw, th_loadstore_width, full_preds, all_v_scalar_const_ptr_ops) +DEF_RVV_FUNCTION (vlbu, th_loadstore_width, full_preds, all_v_scalar_const_ptr_ops) +DEF_RVV_FUNCTION (vlhu, th_loadstore_width, full_preds, all_v_scalar_const_ptr_ops) +DEF_RVV_FUNCTION (vlwu, th_loadstore_width, full_preds, all_v_scalar_const_ptr_ops) +DEF_RVV_FUNCTION (vsb, th_loadstore_width, none_m_preds, all_v_scalar_ptr_ops) +DEF_RVV_FUNCTION (vsh, th_loadstore_width, none_m_preds, all_v_scalar_ptr_ops) +DEF_RVV_FUNCTION (vsw, th_loadstore_width, none_m_preds, all_v_scalar_ptr_ops) +DEF_RVV_FUNCTION (vlsb, th_loadstore_width, full_preds, all_v_scalar_const_ptr_size_ops) +DEF_RVV_FUNCTION (vlsh, th_loadstore_width, full_preds, all_v_scalar_const_ptr_size_ops) +DEF_RVV_FUNCTION (vlsw, th_loadstore_width, full_preds, all_v_scalar_const_ptr_size_ops) +DEF_RVV_FUNCTION (vlsbu, th_loadstore_width, full_preds, all_v_scalar_const_ptr_size_ops) +DEF_RVV_FUNCTION (vlshu, th_loadstore_width, full_preds, all_v_scalar_const_ptr_size_ops) +DEF_RVV_FUNCTION (vlswu, th_loadstore_width, full_preds, all_v_scalar_const_ptr_size_ops) +DEF_RVV_FUNCTION (vssb, th_loadstore_width, none_m_preds, all_v_scalar_ptr_size_ops) +DEF_RVV_FUNCTION (vssh, th_loadstore_width, none_m_preds, all_v_scalar_ptr_size_ops) +DEF_RVV_FUNCTION (vssw, th_loadstore_width, none_m_preds, all_v_scalar_ptr_size_ops) +DEF_RVV_FUNCTION (vlxb, th_indexed_loadstore_width, full_preds, all_v_scalar_const_ptr_index_ops) +DEF_RVV_FUNCTION (vlxh, th_indexed_loadstore_width, full_preds, all_v_scalar_const_ptr_index_ops) +DEF_RVV_FUNCTION (vlxw, th_indexed_loadstore_width, full_preds, all_v_scalar_const_ptr_index_ops) +DEF_RVV_FUNCTION (vlxbu, th_indexed_loadstore_width, full_preds, all_v_scalar_const_ptr_index_ops) +DEF_RVV_FUNCTION (vlxhu, th_indexed_loadstore_width, full_preds, all_v_scalar_const_ptr_index_ops) +DEF_RVV_FUNCTION (vlxwu, th_indexed_loadstore_width, full_preds, all_v_scalar_const_ptr_index_ops) +DEF_RVV_FUNCTION (vsxb, th_indexed_loadstore_width, none_m_preds, all_v_scalar_ptr_index_ops) +DEF_RVV_FUNCTION (vsxh, th_indexed_loadstore_width, none_m_preds, all_v_scalar_ptr_index_ops) +DEF_RVV_FUNCTION (vsxw, th_indexed_loadstore_width, none_m_preds, all_v_scalar_ptr_index_ops) +DEF_RVV_FUNCTION (vsuxb, th_indexed_loadstore_width, none_m_preds, all_v_scalar_ptr_index_ops) +DEF_RVV_FUNCTION (vsuxh, th_indexed_loadstore_width, none_m_preds, all_v_scalar_ptr_index_ops) +DEF_RVV_FUNCTION (vsuxw, th_indexed_loadstore_width, none_m_preds, all_v_scalar_ptr_index_ops) +DEF_RVV_FUNCTION (vext_x_v, th_extract, none_preds, iu_x_s_u_ops) +#undef REQUIRED_EXTENSIONS + +#undef DEF_RVV_FUNCTION diff --git a/gcc/config/riscv/thead-vector.md b/gcc/config/riscv/thead-vector.md index 696b815252d..0f3700d9269 100644 --- a/gcc/config/riscv/thead-vector.md +++ b/gcc/config/riscv/thead-vector.md @@ -1,7 +1,95 @@ (define_c_enum "unspec" [ + UNSPEC_TH_VLB + UNSPEC_TH_VLBU + UNSPEC_TH_VLH + UNSPEC_TH_VLHU + UNSPEC_TH_VLW + UNSPEC_TH_VLWU + + UNSPEC_TH_VLSB + UNSPEC_TH_VLSBU + UNSPEC_TH_VLSH + UNSPEC_TH_VLSHU + UNSPEC_TH_VLSW + UNSPEC_TH_VLSWU + + UNSPEC_TH_VLXB + UNSPEC_TH_VLXBU + UNSPEC_TH_VLXH + UNSPEC_TH_VLXHU + UNSPEC_TH_VLXW + UNSPEC_TH_VLXWU + + UNSPEC_TH_VSUXB + UNSPEC_TH_VSUXH + UNSPEC_TH_VSUXW + UNSPEC_TH_VWLDST ]) +(define_int_iterator UNSPEC_TH_VLMEM_OP [ + UNSPEC_TH_VLB UNSPEC_TH_VLBU + UNSPEC_TH_VLH UNSPEC_TH_VLHU + UNSPEC_TH_VLW UNSPEC_TH_VLWU +]) + +(define_int_iterator UNSPEC_TH_VLSMEM_OP [ + UNSPEC_TH_VLSB UNSPEC_TH_VLSBU + UNSPEC_TH_VLSH UNSPEC_TH_VLSHU + UNSPEC_TH_VLSW UNSPEC_TH_VLSWU +]) + +(define_int_iterator UNSPEC_TH_VLXMEM_OP [ + UNSPEC_TH_VLXB UNSPEC_TH_VLXBU + UNSPEC_TH_VLXH UNSPEC_TH_VLXHU + UNSPEC_TH_VLXW UNSPEC_TH_VLXWU +]) + +(define_int_attr vlmem_op_attr [ + (UNSPEC_TH_VLB "b") (UNSPEC_TH_VLBU "bu") + (UNSPEC_TH_VLH "h") (UNSPEC_TH_VLHU "hu") + (UNSPEC_TH_VLW "w") (UNSPEC_TH_VLWU "wu") + (UNSPEC_TH_VLSB "b") (UNSPEC_TH_VLSBU "bu") + (UNSPEC_TH_VLSH "h") (UNSPEC_TH_VLSHU "hu") + (UNSPEC_TH_VLSW "w") (UNSPEC_TH_VLSWU "wu") + (UNSPEC_TH_VLXB "b") (UNSPEC_TH_VLXBU "bu") + (UNSPEC_TH_VLXH "h") (UNSPEC_TH_VLXHU "hu") + (UNSPEC_TH_VLXW "w") (UNSPEC_TH_VLXWU "wu") + (UNSPEC_TH_VSUXB "b") + (UNSPEC_TH_VSUXH "h") + (UNSPEC_TH_VSUXW "w") +]) + +(define_int_attr vlmem_order_attr [ + (UNSPEC_TH_VLXB "") + (UNSPEC_TH_VLXH "") + (UNSPEC_TH_VLXW "") + (UNSPEC_TH_VSUXB "u") + (UNSPEC_TH_VSUXH "u") + (UNSPEC_TH_VSUXW "u") +]) + +(define_int_iterator UNSPEC_TH_VSMEM_OP [ + UNSPEC_TH_VLB + UNSPEC_TH_VLH + UNSPEC_TH_VLW +]) + +(define_int_iterator UNSPEC_TH_VSSMEM_OP [ + UNSPEC_TH_VLSB + UNSPEC_TH_VLSH + UNSPEC_TH_VLSW +]) + +(define_int_iterator UNSPEC_TH_VSXMEM_OP [ + UNSPEC_TH_VLXB + UNSPEC_TH_VLXH + UNSPEC_TH_VLXW + UNSPEC_TH_VSUXB + UNSPEC_TH_VSUXH + UNSPEC_TH_VSUXW +]) + (define_mode_iterator V_VLS_VT [V VLS VT]) (define_mode_iterator V_VB_VLS_VT [V VB VLS VT]) @@ -100,3 +188,168 @@ } [(set_attr "type" "vldm,vstm,vmalu,vmalu,vmalu") (set_attr "mode" "")]) + +(define_expand "@pred_mov_width" + [(set (match_operand:V_VLS 0 "nonimmediate_operand") + (if_then_else:V_VLS + (unspec: + [(match_operand: 1 "vector_mask_operand") + (match_operand 4 "vector_length_operand") + (match_operand 5 "const_int_operand") + (match_operand 6 "const_int_operand") + (match_operand 7 "const_int_operand") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_TH_VLMEM_OP) + (match_operand:V_VLS 3 "vector_move_operand") + (match_operand:V_VLS 2 "vector_merge_operand")))] + "TARGET_XTHEADVECTOR" + {}) + +(define_insn_and_split "*pred_mov_width" + [(set (match_operand:V_VLS 0 "nonimmediate_operand" "=vr, vr, vd, m, vr, vr") + (if_then_else:V_VLS + (unspec: + [(match_operand: 1 "vector_mask_operand" "vmWc1, Wc1, vm, vmWc1, Wc1, Wc1") + (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK") + (match_operand 5 "const_int_operand" " i, i, i, i, i, i") + (match_operand 6 "const_int_operand" " i, i, i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_TH_VLMEM_OP) + (match_operand:V_VLS 3 "reg_or_mem_operand" " m, m, m, vr, vr, vr") + (match_operand:V_VLS 2 "vector_merge_operand" " 0, vu, vu, vu, vu, 0")))] + "(TARGET_XTHEADVECTOR + && (register_operand (operands[0], mode) + || register_operand (operands[3], mode)))" + "@ + vl.v\t%0,%3%p1 + vl.v\t%0,%3 + vl.v\t%0,%3,%1.t + vs.v\t%3,%0%p1 + vmv.v.v\t%0,%3 + vmv.v.v\t%0,%3" + "&& register_operand (operands[0], mode) + && register_operand (operands[3], mode) + && satisfies_constraint_vu (operands[2]) + && INTVAL (operands[7]) == riscv_vector::VLMAX" + [(set (match_dup 0) (match_dup 3))] + "" + [(set_attr "type" "vlde,vlde,vlde,vste,vimov,vimov") + (set_attr "mode" "")]) + +(define_insn "@pred_store_width" + [(set (match_operand:VI 0 "memory_operand" "+m") + (if_then_else:VI + (unspec: + [(match_operand: 1 "vector_mask_operand" "vmWc1") + (match_operand 3 "vector_length_operand" " rK") + (match_operand 4 "const_int_operand" " i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_TH_VSMEM_OP) + (match_operand:VI 2 "register_operand" " vr") + (match_dup 0)))] + "TARGET_XTHEADVECTOR" + "vs.v\t%2,%0%p1" + [(set_attr "type" "vste") + (set_attr "mode" "") + (set (attr "avl_type_idx") (const_int 4)) + (set_attr "vl_op_idx" "3")]) + +(define_insn "@pred_strided_load_width" + [(set (match_operand:VI 0 "register_operand" "=vr, vr, vd") + (if_then_else:VI + (unspec: + [(match_operand: 1 "vector_mask_operand" "vmWc1, Wc1, vm") + (match_operand 5 "vector_length_operand" " rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i") + (match_operand 7 "const_int_operand" " i, i, i") + (match_operand 8 "const_int_operand" " i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_TH_VLSMEM_OP) + (unspec:VI + [(match_operand:VI 3 "memory_operand" " m, m, m") + (match_operand 4 "pmode_reg_or_0_operand" " rJ, rJ, rJ")] UNSPEC_TH_VLSMEM_OP) + (match_operand:VI 2 "vector_merge_operand" " 0, vu, vu")))] + "TARGET_XTHEADVECTOR" + "vls.v\t%0,%3,%z4%p1" + [(set_attr "type" "vlds") + (set_attr "mode" "")]) + +(define_insn "@pred_strided_store_width" + [(set (match_operand:VI 0 "memory_operand" "+m") + (if_then_else:VI + (unspec: + [(match_operand: 1 "vector_mask_operand" "vmWc1") + (match_operand 4 "vector_length_operand" " rK") + (match_operand 5 "const_int_operand" " i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_TH_VSSMEM_OP) + (unspec:VI + [(match_operand 2 "pmode_reg_or_0_operand" " rJ") + (match_operand:VI 3 "register_operand" " vr")] UNSPEC_TH_VSSMEM_OP) + (match_dup 0)))] + "TARGET_XTHEADVECTOR" + "vss.v\t%3,%0,%z2%p1" + [(set_attr "type" "vsts") + (set_attr "mode" "") + (set (attr "avl_type_idx") (const_int 5))]) + +(define_insn "@pred_indexed_load_width" + [(set (match_operand:VI 0 "register_operand" "=vd, vr,vd, vr") + (if_then_else:VI + (unspec: + [(match_operand: 1 "vector_mask_operand" " vm,Wc1,vm,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK,rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_TH_VLXMEM_OP) + (unspec:VI + [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ,rJ, rJ") + (mem:BLK (scratch)) + (match_operand:VI 4 "register_operand" " vr, vr,vr, vr")] UNSPEC_TH_VLXMEM_OP) + (match_operand:VI 2 "vector_merge_operand" " vu, vu, 0, 0")))] + "TARGET_XTHEADVECTOR" + "vlx.v\t%0,(%z3),%4%p1" + [(set_attr "type" "vldux") + (set_attr "mode" "")]) + +(define_insn "@pred_indexed_store_width" + [(set (mem:BLK (scratch)) + (unspec:BLK + [(unspec: + [(match_operand: 0 "vector_mask_operand" "vmWc1") + (match_operand 4 "vector_length_operand" " rK") + (match_operand 5 "const_int_operand" " i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_TH_VSXMEM_OP) + (match_operand 1 "pmode_reg_or_0_operand" " rJ") + (match_operand:VI 2 "register_operand" " vr") + (match_operand:VI 3 "register_operand" " vr")] UNSPEC_TH_VSXMEM_OP))] + "TARGET_XTHEADVECTOR" + "vsx.v\t%3,(%z1),%2%p0" + [(set_attr "type" "vstux") + (set_attr "mode" "")]) + +(define_expand "@pred_th_extract" + [(set (match_operand: 0 "register_operand") + (unspec: + [(vec_select: + (match_operand:V_VLSI 1 "register_operand") + (parallel [(match_operand:DI 2 "register_operand" "r")])) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))] + "TARGET_XTHEADVECTOR" +{}) + +(define_insn "*pred_th_extract" + [(set (match_operand: 0 "register_operand" "=r") + (unspec: + [(vec_select: + (match_operand:V_VLSI 1 "register_operand" "vr") + (parallel [(match_operand:DI 2 "register_operand" "r")])) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))] + "TARGET_XTHEADVECTOR" + "vext.x.v\t%0,%1,%2" + [(set_attr "type" "vimovvx") + (set_attr "mode" "")]) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c new file mode 100644 index 00000000000..3c12c124597 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** th.vsetivli\tzero,4,e32,m1,tu,ma +** th.vlb\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vlb\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** th.vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** th.vsb\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out) +{ + vint32m1_t v = __riscv_th_vlb_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_th_vlb_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vadd_vv_i32m1 (v2, v2, 4); + vint32m1_t v4 = __riscv_vadd_vv_i32m1_tu (v3, v2, v2, 4); + __riscv_th_vsb_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vsetivli\tzero,4,e32,m1,ta,ma +** th.vlb.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** th.vadd\.vv\tv[1-9][0-9]?,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t +** th.vsb.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_th_vlb_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_th_vlb_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vadd_vv_i32m1 (v2, v2, 4); + vint32m1_t v4 = __riscv_vadd_vv_i32m1_m (mask, v3, v3, 4); + __riscv_th_vsb_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vsetivli\tzero,4,e32,m1,tu,mu +** th.vlb\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vlb.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** th.vadd\.vv\tv[1-9][0-9]?,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t +** th.vsb.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_th_vlb_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_th_vlb_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vadd_vv_i32m1 (v2, v2, 4); + vint32m1_t v4 = __riscv_vadd_vv_i32m1_tumu (mask, v3, v2, v2, 4); + __riscv_th_vsb_v_i32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c new file mode 100644 index 00000000000..30bef369375 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** th.vsetivli\tzero,4,e32,m1,tu,ma +** th.vlbu\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vlbu\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vsb\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, uint32_t x) +{ + vuint32m1_t v = __riscv_th_vlbu_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_th_vlbu_v_u32m1_tu (v, in, 4); + vuint32m1_t v3 = __riscv_vadd_vx_u32m1 (v2, -16, 4); + vuint32m1_t v4 = __riscv_vadd_vx_u32m1_tu (v3, v2, -16, 4); + __riscv_th_vsb_v_u32m1 (out, v4, 4); +} + +/* +** f2: +** th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vsetivli\tzero,4,e32,m1,ta,ma +** th.vlbu.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t +** th.vsb.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, uint32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vuint32m1_t v = __riscv_th_vlbu_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_th_vlbu_v_u32m1_m (mask, in, 4); + vuint32m1_t v3 = __riscv_vadd_vx_u32m1 (v2, -16, 4); + vuint32m1_t v4 = __riscv_vadd_vx_u32m1_m (mask, v3, -16, 4); + __riscv_th_vsb_v_u32m1 (out, v4, 4); +} + +/* +** f3: +** th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vsetivli\tzero,4,e32,m1,tu,mu +** th.vlbu\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vlbu.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t +** th.vsb.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, uint32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vuint32m1_t v = __riscv_th_vlbu_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_th_vlbu_v_u32m1_tumu (mask, v, in, 4); + vuint32m1_t v3 = __riscv_vadd_vx_u32m1 (v2, -16, 4); + vuint32m1_t v4 = __riscv_vadd_vx_u32m1_tumu (mask, v3, v2, -16, 4); + __riscv_th_vsb_v_u32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c new file mode 100644 index 00000000000..3c8b5ccc16b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** th.vsetivli\tzero,4,e32,m1,tu,ma +** th.vlh\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vlh\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vsh\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vint32m1_t v = __riscv_th_vlh_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_th_vlh_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vadd_vx_i32m1 (v2, -16, 4); + vint32m1_t v4 = __riscv_vadd_vx_i32m1_tu (v3, v2, -16, 4); + __riscv_th_vsh_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vsetivli\tzero,4,e32,m1,ta,ma +** th.vlh.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t +** th.vsh.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_th_vlh_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_th_vlh_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vadd_vx_i32m1 (v2, -16, 4); + vint32m1_t v4 = __riscv_vadd_vx_i32m1_m (mask, v3, -16, 4); + __riscv_th_vsh_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vsetivli\tzero,4,e32,m1,tu,mu +** th.vlh\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vlh.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t +** th.vsh.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_th_vlh_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_th_vlh_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vadd_vx_i32m1 (v2, -16, 4); + vint32m1_t v4 = __riscv_vadd_vx_i32m1_tumu (mask, v3, v2, -16, 4); + __riscv_th_vsh_v_i32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c new file mode 100644 index 00000000000..b7c00404f18 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** th.vsetivli\tzero,4,e32,m1,tu,ma +** th.vlhu\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vlhu\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vsh\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, uint32_t x) +{ + vuint32m1_t v = __riscv_th_vlhu_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_th_vlhu_v_u32m1_tu (v, in, 4); + vuint32m1_t v3 = __riscv_vadd_vx_u32m1 (v2, -16, 4); + vuint32m1_t v4 = __riscv_vadd_vx_u32m1_tu (v3, v2, -16, 4); + __riscv_th_vsh_v_u32m1 (out, v4, 4); +} + +/* +** f2: +** th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vsetivli\tzero,4,e32,m1,ta,ma +** th.vlhu.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t +** th.vsh.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, uint32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vuint32m1_t v = __riscv_th_vlhu_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_th_vlhu_v_u32m1_m (mask, in, 4); + vuint32m1_t v3 = __riscv_vadd_vx_u32m1 (v2, -16, 4); + vuint32m1_t v4 = __riscv_vadd_vx_u32m1_m (mask, v3, -16, 4); + __riscv_th_vsh_v_u32m1 (out, v4, 4); +} + +/* +** f3: +** th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vsetivli\tzero,4,e32,m1,tu,mu +** th.vlhu\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vlhu.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t +** th.vsh.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, uint32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vuint32m1_t v = __riscv_th_vlhu_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_th_vlhu_v_u32m1_tumu (mask, v, in, 4); + vuint32m1_t v3 = __riscv_vadd_vx_u32m1 (v2, -16, 4); + vuint32m1_t v4 = __riscv_vadd_vx_u32m1_tumu (mask, v3, v2, -16, 4); + __riscv_th_vsh_v_u32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c new file mode 100644 index 00000000000..17a53012acf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** th.vsetivli\tzero,4,e32,m1,tu,ma +** th.vlw\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vlw\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vsw\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, int32_t x) +{ + vint32m1_t v = __riscv_th_vlw_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_th_vlw_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vadd_vx_i32m1 (v2, x, 4); + vint32m1_t v4 = __riscv_vadd_vx_i32m1_tu (v3, v2, x, 4); + __riscv_th_vsw_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vsetivli\tzero,4,e32,m1,ta,ma +** th.vlw.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vadd\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vsw.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_th_vlw_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_th_vlw_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vadd_vx_i32m1 (v2, x, 4); + vint32m1_t v4 = __riscv_vadd_vx_i32m1_m (mask, v3, x, 4); + __riscv_th_vsw_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vsetivli\tzero,4,e32,m1,tu,mu +** th.vlw\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vlw.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** th.vadd\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** th.vsw.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_th_vlw_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_th_vlw_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vadd_vx_i32m1 (v2, x, 4); + vint32m1_t v4 = __riscv_vadd_vx_i32m1_tumu (mask, v3, v2, x, 4); + __riscv_th_vsw_v_i32m1 (out, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c new file mode 100644 index 00000000000..b187cfc852b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_th_vector.h" + +/* +** f1: +** th.vsetivli\tzero,4,e32,m1,tu,ma +** th.vlwu\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vlwu\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vsw\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out, uint32_t x) +{ + vuint32m1_t v = __riscv_th_vlwu_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_th_vlwu_v_u32m1_tu (v, in, 4); + vuint32m1_t v3 = __riscv_vadd_vx_u32m1 (v2, -16, 4); + vuint32m1_t v4 = __riscv_vadd_vx_u32m1_tu (v3, v2, -16, 4); + __riscv_th_vsw_v_u32m1 (out, v4, 4); +} + +/* +** f2: +** th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vsetivli\tzero,4,e32,m1,ta,ma +** th.vlwu.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t +** th.vsw.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out, uint32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vuint32m1_t v = __riscv_th_vlwu_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_th_vlwu_v_u32m1_m (mask, in, 4); + vuint32m1_t v3 = __riscv_vadd_vx_u32m1 (v2, -16, 4); + vuint32m1_t v4 = __riscv_vadd_vx_u32m1_m (mask, v3, -16, 4); + __riscv_th_vsw_v_u32m1 (out, v4, 4); +} + +/* +** f3: +** th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vsetivli\tzero,4,e32,m1,tu,mu +** th.vlwu\.v\tv[0-9]+,0\([a-x0-9]+\) +** th.vlwu.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** th.vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t +** th.vsw.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out, uint32_t x) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vuint32m1_t v = __riscv_th_vlwu_v_u32m1 (in, 4); + vuint32m1_t v2 = __riscv_th_vlwu_v_u32m1_tumu (mask, v, in, 4); + vuint32m1_t v3 = __riscv_vadd_vx_u32m1 (v2, -16, 4); + vuint32m1_t v4 = __riscv_vadd_vx_u32m1_tumu (mask, v3, v2, -16, 4); + __riscv_th_vsw_v_u32m1 (out, v4, 4); +}