From patchwork Sun Jun 12 06:41:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Takayuki 'January June' Suwa X-Patchwork-Id: 55039 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 6D66F38418AF for ; Sun, 12 Jun 2022 06:46:47 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 6D66F38418AF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1655016407; bh=YqCdh9+CIjvR8nmAyN2laArFJ59oMzG4Epqs1D3AlvE=; h=Date:To:Subject:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=gKdR7v01IWhfoNKFhM+3BN4hCHgo5WLdVZxQyEBFq+zLc0pilruy2QPicekjeA5td nDsi5Jap1wFFvcRGcLQ3DHUNXYIYVYzE+SBT1O1/FEnOCeoicthioxRvlE3HJbmcak 0nmHCw3RIMVegLEdRv/6w4vhogg9g+8I/d+1Fw8E= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from nh602-vm5.bullet.mail.ssk.yahoo.co.jp (nh602-vm5.bullet.mail.ssk.yahoo.co.jp [182.22.90.30]) by sourceware.org (Postfix) with SMTP id 26B1B386F0F1 for ; Sun, 12 Jun 2022 06:43:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 26B1B386F0F1 Received: from [182.22.66.104] by nh602.bullet.mail.ssk.yahoo.co.jp with NNFMP; 12 Jun 2022 06:43:19 -0000 Received: from [182.22.91.129] by t602.bullet.mail.ssk.yahoo.co.jp with NNFMP; 12 Jun 2022 06:43:19 -0000 Received: from [127.0.0.1] by omp602.mail.ssk.yahoo.co.jp with NNFMP; 12 Jun 2022 06:43:19 -0000 X-Yahoo-Newman-Property: ymail-3 X-Yahoo-Newman-Id: 318122.26426.bm@omp602.mail.ssk.yahoo.co.jp Received: (qmail 31837 invoked by alias); 12 Jun 2022 06:43:19 -0000 Received: from unknown (HELO ?192.168.2.3?) (175.177.45.176 with ) by smtp6005.mail.ssk.ynwp.yahoo.co.jp with SMTP; 12 Jun 2022 06:43:19 -0000 X-YMail-JAS: DdivIhoVM1lLCT57qeIvV0LbJSmddvG54lOvk6SIGTFJS8zprIkXB.lB7fhjYNB_F7vA1yPqabg3OtkxUipuDGJINyXFjBFdHCWl6npsiG8JXoyuIfy93QMYPFjbU8d.x3.bx7BSbA-- X-Apparently-From: X-YMail-OSG: 0VCuYMoVM1m0Ns6cYuWtDNuY_egJkoyUP6FrtjKIKp1KEbI 5i5mZClkmoksb1wivtuMGOQzkGvZlrpA14uAwPYwvy79mfjsoOVfqVjJb1GX 8773X8a1MMecMxQucHOYblXcROtHmApHWz2gTsubNKtZiqQo39x1Arec9cKR JmWO_CsE3BPlvAnq9Yb0vHYm21kDswbP5ENPPGXhGkiLBBKS1L3hoxfS3Wcg P9dNlP6FbvFTjGO7ODoucEwdSug7S1uDFU7Bu2b3NeJpVwr8AL6yFf9QL5XV byPEidl6AcKfFDdL6xUJtFYW6.faJWRt9QKUq6gAL2D8SIjMYzDWOglsDp6b dMvx0G3BHDkZsyj5tAcij6efeQLhAwQ2997oF3kqAXqpCSh5bg83WKYYGAzh c.968vDIvFfGJ_VX2zu5mu1pOto.uLhodU3wkD.IPzmVfRb.feYJ9tsKm194 PLgdkafiNhzy15vIp4LFmoDR4BLpUE3H65_7dORysnLwi0OPbf7B85FxmQ.8 THhMYpNy9wBX6uJhmGipKFnNxH3bXigNyaImR8CGF2BwlZboT8q_Z8Idg2If F2.NSyUeJpKn9A0GyoTA_VnNQPQSYzqjX_QuJad3Sm1IDTHqonwBIzbfr9gB SEFGeYrZGgC87SaYaCmJnKOnbngW3YfnOPfqnDlsCAi83YHcn_vjsFzQBXxx GgHaB8LCQSmcvNFgfuk1w2wpXW2sy8xG0FKxxgJtixBd22FU4nyY15pXivAI zTEGQuBIT37fFmRGLWKo6NgGd0O2AjDUIrN9zK3IUGfMOaZOxcB0b8zSKMRA IWxgUXRIfTZduTSKlMBkeyy8uJeYarnpE.EBTo3KlSvCFSsIZ1cK0Vz0sIWH dQwAbV_Ax586MsKpCJBzjqyOR9aGrGkktic4_0VlKLxpEoEHUviFFjX2j2qL ZSZnxE6UyUBpWOZD5yg-- Message-ID: Date: Sun, 12 Jun 2022 15:41:56 +0900 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 6.1; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Content-Language: en-US To: GCC Patches Subject: [PATCH 4/4] xtensa: Optimize bitwise AND operation with some specific forms of constants X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Takayuki 'January June' Suwa via Gcc-patches From: Takayuki 'January June' Suwa Reply-To: Takayuki 'January June' Suwa Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This patch offers several insn-and-split patterns for bitwise AND with register and constant that cannot fit into a "MOVI Ax, simm12" instruction, but can be represented as: i. 1's least significant N bits and the others 0's (17 <= N <= 31) ii. 1's most significant N bits and the others 0's (12 <= N <= 31) iii. M 1's sequence of bits and trailing N 0's bits (1 <= M <= 16, 1 <= N <= 30) And also offers shortcuts for conditional branch if each of the abovementioned operations is (not) equal to zero. gcc/ChangeLog: * config/xtensa/predicates.md (shifted_mask_operand): New predicate. * config/xtensa/xtensa.md (*andsi3_const_pow2_minus_one): New insn-and-split pattern. (*andsi3_const_negative_pow2, *andsi3_const_shifted_mask, *masktrue_const_pow2_minus_one, *masktrue_const_negative_pow2, *masktrue_const_shifted_mask): Ditto. --- gcc/config/xtensa/predicates.md | 11 +++ gcc/config/xtensa/xtensa.md | 165 ++++++++++++++++++++++++++++++++ 2 files changed, 176 insertions(+) diff --git a/gcc/config/xtensa/predicates.md b/gcc/config/xtensa/predicates.md index bcc83ada0ae..24c77f343a0 100644 --- a/gcc/config/xtensa/predicates.md +++ b/gcc/config/xtensa/predicates.md @@ -52,6 +52,17 @@ (match_test "xtensa_mask_immediate (INTVAL (op))")) (match_operand 0 "register_operand"))) +(define_predicate "shifted_mask_operand" + (and (match_code "const_int") + (match_test "!xtensa_simm12b (INTVAL (op))")) +{ + HOST_WIDE_INT mask = INTVAL (op); + int shift = ctz_hwi (mask); + + return IN_RANGE (shift, 1, 31) + && xtensa_mask_immediate ((uint32_t)mask >> shift); +}) + (define_predicate "extui_fldsz_operand" (and (match_code "const_int") (match_test "IN_RANGE (INTVAL (op), 1, 16)"))) diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md index 090a2939684..286a1d8c38e 100644 --- a/gcc/config/xtensa/xtensa.md +++ b/gcc/config/xtensa/xtensa.md @@ -645,6 +645,78 @@ (set_attr "mode" "SI") (set_attr "length" "6")]) +(define_insn_and_split "*andsi3_const_pow2_minus_one" + [(set (match_operand:SI 0 "register_operand" "=a") + (and:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "const_int_operand" "i")))] + "IN_RANGE (exact_log2 (INTVAL (operands[2]) + 1), 17, 31)" + "#" + "&& 1" + [(set (match_dup 0) + (ashift:SI (match_dup 1) + (match_dup 2))) + (set (match_dup 0) + (lshiftrt:SI (match_dup 0) + (match_dup 2)))] +{ + operands[2] = GEN_INT (32 - floor_log2 (INTVAL (operands[2]) + 1)); +} + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set (attr "length") + (if_then_else (match_test "TARGET_DENSITY + && INTVAL (operands[2]) == 0x7FFFFFFF") + (const_int 5) + (const_int 6)))]) + +(define_insn_and_split "*andsi3_const_negative_pow2" + [(set (match_operand:SI 0 "register_operand" "=a") + (and:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "const_int_operand" "i")))] + "IN_RANGE (exact_log2 (-INTVAL (operands[2])), 12, 31)" + "#" + "&& 1" + [(set (match_dup 0) + (lshiftrt:SI (match_dup 1) + (match_dup 2))) + (set (match_dup 0) + (ashift:SI (match_dup 0) + (match_dup 2)))] +{ + operands[2] = GEN_INT (floor_log2 (-INTVAL (operands[2]))); +} + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "6")]) + +(define_insn_and_split "*andsi3_const_shifted_mask" + [(set (match_operand:SI 0 "register_operand" "=a") + (and:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "shifted_mask_operand" "i")))] + "" + "#" + "" + [(set (match_dup 0) + (zero_extract:SI (match_dup 1) + (match_dup 3) + (match_dup 2))) + (set (match_dup 0) + (ashift:SI (match_dup 0) + (match_dup 2)))] +{ + HOST_WIDE_INT mask = INTVAL (operands[2]); + int shift = ctz_hwi (mask); + operands[2] = GEN_INT (shift); + operands[3] = GEN_INT (floor_log2 (((uint32_t)mask >> shift) + 1)); +} + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set (attr "length") + (if_then_else (match_test "TARGET_DENSITY + && ctz_hwi (INTVAL (operands[2])) == 1") + (const_int 5) + (const_int 6)))]) + (define_insn "iorsi3" [(set (match_operand:SI 0 "register_operand" "=a") (ior:SI (match_operand:SI 1 "register_operand" "%r") @@ -1648,6 +1720,99 @@ (set_attr "mode" "none") (set_attr "length" "3")]) +(define_insn_and_split "*masktrue_const_pow2_minus_one" + [(set (pc) + (if_then_else (match_operator 4 "boolean_operator" + [(zero_extract:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "const_int_operand" "i") + (const_int 0)) + (const_int 0)]) + (label_ref (match_operand 3 "" "")) + (pc))) + (clobber (match_scratch:SI 0 "=&a"))] + "IN_RANGE (INTVAL (operands[2]), 17, 31)" + "#" + "&& reload_completed" + [(set (match_dup 0) + (ashift:SI (match_dup 1) + (match_dup 2))) + (set (pc) + (if_then_else (match_op_dup 4 + [(match_dup 0) + (const_int 0)]) + (label_ref (match_dup 3)) + (pc)))] +{ + operands[2] = GEN_INT (32 - INTVAL (operands[2])); +} + [(set_attr "type" "jump") + (set_attr "mode" "none") + (set (attr "length") + (if_then_else (match_test "TARGET_DENSITY + && INTVAL (operands[2]) == 31") + (const_int 5) + (const_int 6)))]) + +(define_insn_and_split "*masktrue_const_negative_pow2" + [(set (pc) + (if_then_else (match_operator 4 "boolean_operator" + [(and:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "const_int_operand" "i")) + (const_int 0)]) + (label_ref (match_operand 3 "" "")) + (pc))) + (clobber (match_scratch:SI 0 "=&a"))] + "IN_RANGE (exact_log2 (-INTVAL (operands[2])), 12, 30)" + "#" + "&& reload_completed" + [(set (match_dup 0) + (lshiftrt:SI (match_dup 1) + (match_dup 2))) + (set (pc) + (if_then_else (match_op_dup 4 + [(match_dup 0) + (const_int 0)]) + (label_ref (match_dup 3)) + (pc)))] +{ + operands[2] = GEN_INT (floor_log2 (-INTVAL (operands[2]))); +} + [(set_attr "type" "jump") + (set_attr "mode" "none") + (set_attr "length" "6")]) + +(define_insn_and_split "*masktrue_const_shifted_mask" + [(set (pc) + (if_then_else (match_operator 4 "boolean_operator" + [(and:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "shifted_mask_operand" "i")) + (const_int 0)]) + (label_ref (match_operand 3 "" "")) + (pc))) + (clobber (match_scratch:SI 0 "=&a"))] + "" + "#" + "reload_completed" + [(set (match_dup 0) + (zero_extract:SI (match_dup 1) + (match_dup 5) + (match_dup 2))) + (set (pc) + (if_then_else (match_op_dup 4 + [(match_dup 0) + (const_int 0)]) + (label_ref (match_dup 3)) + (pc)))] +{ + HOST_WIDE_INT mask = INTVAL (operands[2]); + int shift = ctz_hwi (mask); + operands[2] = GEN_INT (shift); + operands[5] = GEN_INT (floor_log2 (((uint32_t)mask >> shift) + 1)); +} + [(set_attr "type" "jump") + (set_attr "mode" "none") + (set_attr "length" "6")]) + ;; Zero-overhead looping support.