diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc
index bc1580f051b..5c964403257 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -1710,10 +1710,6 @@ rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
 	location_t loc;
 	gimple_seq stmts = NULL;
 	arg0 = gimple_call_arg (stmt, 0);
-	tree arg0_type = TREE_TYPE (arg0);
-	if (INTEGRAL_TYPE_P (TREE_TYPE (arg0_type))
-	    && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (arg0_type)))
-	  return false;
 	arg1 = gimple_call_arg (stmt, 1);
 	tree arg1_type = TREE_TYPE (arg1);
 	tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1));
diff --git a/gcc/testsuite/gcc.target/powerpc/pr121867.c b/gcc/testsuite/gcc.target/powerpc/pr121867.c
new file mode 100644
index 00000000000..0c8f3f8372c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr121867.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-maltivec -mdejagnu-cpu=power8 -O2 -mvsx " } */
+
+/*  This test ensures that we use GIMPLE folding when the element value exceeds
+    the element bit width. It performs modulo reduction and uses vspltis[bhw]
+    to broadcast the value, instead of storing it in memory and performing a
+    shift operation.  */
+
+#include <altivec.h>
+
+vector unsigned char shlb(vector unsigned char in)
+{
+    return vec_sl(in, vec_splats((unsigned char)35));
+}
+
+vector unsigned short shlh(vector unsigned short in)
+{
+    return vec_sl(in, vec_splats((unsigned short)18));
+}
+
+vector unsigned int shlw(vector unsigned int in)
+{
+    return vec_sl(in, vec_splats((unsigned int)34));
+}
+
+/* { dg-final { scan-assembler-times {\mvspltis[bhw]\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mvsl[bhw]\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mlvx\M} 0 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr86731-longlong.c b/gcc/testsuite/gcc.target/powerpc/pr86731-longlong.c
index c97cb49de8c..77cb328d3c2 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr86731-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr86731-longlong.c
@@ -21,10 +21,9 @@ vector signed long long splats4(void)
 }
 
 /* Codegen will consist of splat and shift instructions for most types.
-   Noted variations:  if gimple folding is disabled, or if -fwrapv is not
-   specified, the long long tests will generate a vspltisw+vsld pair,
-   versus generating a single lvx.  */
-/* { dg-final { scan-assembler-times {\mvspltis[bhw]\M|\mxxspltib\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mvsl[bhwd]\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mlvx\M} 0 } } */
+   Now folding is enabled, the vec_sl tests using vector long long type will
+   generate a lvx instead of a vspltisw+vsld pair.  */
 
+/* { dg-final { scan-assembler-times {\mvspltis[bhw]\M} 0 } } */
+/* { dg-final { scan-assembler-times {\mvsl[bhwd]\M} 0 } } */
+/* { dg-final { scan-assembler-times {\mlvx\M} 2 } } */